EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 197

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

16.4 Register Map
16.5 Register Description
16.5.1 USARTn_CTRL - Control Register
31:29
28
Offset
0x000
0x004
0x008
0x00C
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
0x034
0x038
0x03C
0x040
0x044
0x048
0x04C
0x050
0x054
Offset
0x000
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
The offset register address is relative to the registers base address.
Reserved
BYTESWAP
Set to switch the order of the bytes in double accesses.
Name
Value
0
1
Name
USARTn_CTRL
USARTn_FRAME
USARTn_TRIGCTRL
USARTn_CMD
USARTn_STATUS
USARTn_CLKDIV
USARTn_RXDATAX
USARTn_RXDATA
USARTn_RXDOUBLEX
USARTn_RXDOUBLE
USARTn_RXDATAXP
USARTn_RXDOUBLEXP
USARTn_TXDATAX
USARTn_TXDATA
USARTn_TXDOUBLEX
USARTn_TXDOUBLE
USARTn_IF
USARTn_IFS
USARTn_IFC
USARTn_IEN
USARTn_IRCTRL
USARTn_ROUTE
Description
Normal byte order
Byte order swapped
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
Access
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197
Bit Position
Type
RW
RW
RW
W1
R
RW
R
R
R
R
R
R
W
W
W
W
R
W1
W1
RW
RW
RW
Byteswap In Double Accesses
Description
Description
Control Register
USART Frame Format Register
USART Trigger Control register
Command Register
USART Status Register
Clock Control Register
RX Buffer Data Extended Register
RX Buffer Data Register
RX Buffer Double Data Extended Register
RX FIFO Double Data Register
RX Buffer Data Extended Peek Register
RX Buffer Double Data Extended Peek Register
TX Buffer Data Extended Register
TX Buffer Data Register
TX Buffer Double Data Extended Register
TX Buffer Double Data Register
Interrupt Flag Register
Interrupt Flag Set Register
Interrupt Flag Clear Register
Interrupt Enable Register
IrDA Control Register
I/O Routing Register
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