EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 240

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.5.18 LEUARTn_SYNCBUSY - Synchronization Busy Register
31:1
0
31:8
7
6
5
4
3
2
1
0
Bit
Offset
0x044
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
REGFREEZE
When set, the update of the LEUART is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Reserved
PULSECTRL
Set when the value written to LEUARTn_PULSECTRL is being synchronized.
TXDATA
Set when the value written to LEUARTn_TXDATA is being synchronized.
TXDATAX
Set when the value written to LEUARTn_TXDATAX is being synchronized.
SIGFRAME
Set when the value written to LEUARTn_SIGFRAME is being synchronized.
STARTFRAME
Set when the value written to LEUARTn_STARTFRAME is being synchronized.
CLKDIV
Set when the value written to LEUARTn_CLKDIV is being synchronized.
CMD
Set when the value written to LEUARTn_CMD is being synchronized.
CTRL
Set when the value written to LEUARTn_CTRL is being synchronized.
Name
Name
Value
0
1
Mode
UPDATE
FREEZE
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
R
R
R
R
R
R
R
R
Access
Access
Description
Each write access to a LEUART register is updated into the Low Frequency domain
as soon as possible.
The LEUART is not updated with the new written value.
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240
Bit Position
Register Update Freeze
LEUARTn_PULSECTRL Register Busy
LEUARTn_TXDATA Register Busy
LEUARTn_TXDATAX Register Busy
LEUARTn_SIGFRAME Register Busy
LEUARTn_STARTFRAME Register Busy
LEUARTn_CLKDIV Register Busy
LEUARTn_CMD Register Busy
LEUARTn_CTRL Register Busy
Description
Description
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