EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 183

MCU 32BIT 16KB FLASH 32-QFN

EFM32G200F16

Manufacturer Part Number
EFM32G200F16
Description
MCU 32BIT 16KB FLASH 32-QFN
Manufacturer
Energy Micro
Series
Geckor
Datasheets

Specifications of EFM32G200F16

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.8 V
Data Converters
A/D 4x12b, D/A 1x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad
Processor Series
EFM32G200
Core
ARM Cortex-M3
Data Bus Width
32 bit
Data Ram Size
8 KB
Interface Type
I2C, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
24
Number Of Timers
2
Operating Supply Voltage
1.8 V to 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
16.3.2.4.2 Blocking Incoming Data
16.3.2.4.3 Clock Recovery and Filtering
2010-09-06 - d0001_Rev1.00
Figure 16.4. USART Receive Buffer Operation
The receive buffer, including the receive shift register can be cleared by setting CLEARRX in
USARTn_CMD. Any frame currently being received will not be discarded.
When using hardware frame recognition, as detailed in Section 16.3.2.8 (p. 188)
Section 16.3.2.9 (p. 189) , it is necessary to be able to let the receiver sample incoming frames without
passing the frames to software by loading them into the receive buffer. This is accomplished by blocking
incoming data.
Incoming data is blocked as long as RXBLOCK in USARTn_STATUS is set. When blocked, frames
received by the receiver will not be loaded into the receive buffer, and software is not notified by the
RXDATAV flag in USARTn_STATUS or the RXDATAV interrupt flag in USARTn_IF at their arrival. For
data to be loaded into the receive buffer, RXBLOCK must be cleared in the instant a frame is fully
received by the receiver. RXBLOCK is set by setting RXBLOCKEN in USARTn_CMD and disabled by
setting RXBLOCKDIS also in USARTn_CMD. There is one exception where data is loaded into the
receive buffer even when RXBLOCK is set. This is when an address frame is received when operating
in multi-processor mode. See Section 16.3.2.8 (p. 188) for more information.
Frames received containing framing or parity errors will not result in the FERR and PERR interrupt
flags in USARTn_IF being set while RXBLOCK in USARTn_STATUS is set. Hardware recognition is not
applied to these erroneous frames, and they are silently discarded.
Note
The receiver samples the incoming signal at a rate 16, 8, 6 or 4 times higher than the given baud rate,
depending on the oversampling mode given by OVS in USARTn_CTRL. Lower oversampling rates make
higher baud rates possible, but give less room for errors.
When a high-to-low transition is registered on the input while the receiver is idle, this is recognized as a
start-bit, and the baud rate generator is synchronized with the incoming frame.
For oversampling modes 16, 8 and 6, every bit in the incoming frame is sampled three times to gain
a level of noise immunity. These samples are aimed at the middle of the bit-periods, as visualized in
RXDOUBLE
RXDOUBLEX
RXDOUBLEXP
If a frame is received while RXBLOCK in USARTn_STATUS is cleared, but stays in the
receive shift register because the receive buffer is full, the received frame will be loaded into
the receive buffer when space becomes available even if RXBLOCK is set at that time.
The overflow interrupt flag RXOF in USARTn_IF will be set if a frame in the receive shift
register, waiting to be loaded into the receive buffer is overwritten by an incoming frame
even though RXBLOCK in USARTn_STATUS is set.
RX buffer elem ent 0
RX buffer elem ent 1
Shift register
Status
Status
Status
Peripheral Bus
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RXDATA,
RXDATAX,
RXDATAXP
and

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