EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 442

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

29.5.20 LCD_FREEZE - Freeze Register
29.5.21 LCD_SYNCBUSY - Synchronization Busy Register
31:1
0
31:12
11
10
9
8
7
6
5
4
Offset
0x060
Reset
Access
Name
Bit
Offset
0x064
Reset
Access
Name
Bit
2010-09-06 - d0001_Rev1.00
Reserved
REGFREEZE
When set, the update of the LCD is postponed until this bit is cleared. Use this bit to update several registers simultaneously.
Reserved
SEGD3H
Set when the value written to LCD_SEGD3H is being synchronized.
SEGD2H
Set when the value written to LCD_SEGD2H is being synchronized.
SEGD1H
Set when the value written to LCD_SEGD1H is being synchronized.
SEGD0H
Set when the value written to LCD_SEGD0H is being synchronized.
SEGD3L
Set when the value written to LCD_SEGD3L is being synchronized.
SEGD2L
Set when the value written to LCD_SEGD2L is being synchronized.
SEGD1L
Set when the value written to LCD_SEGD1L is being synchronized.
SEGD0L
Set when the value written to LCD_SEGD0L is being synchronized.
Name
Name
Value
0
1
Mode
UPDATE
FREEZE
0
0
0
0
0
0
0
0
0
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
Reset
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
RW
R
R
R
R
R
R
R
R
Access
Access
Description
Each write access to an LCD register is updated into the Low Frequency domain as
soon as possible.
The LCD is not updated with the new written value.
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442
Bit Position
Bit Position
Register Update Freeze
LCD_SEGD3H Register Busy
LCD_SEGD2H Register Busy
LCD_SEGD1H Register Busy
LCD_SEGD0H Register Busy
LCD_SEGD3L Register Busy
LCD_SEGD2L Register Busy
LCD_SEGD1L Register Busy
LCD_SEGD0L Register Busy
Description
Description
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