EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 155

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.8 Bus States
15.3.9 Slave Operation
2010-09-06 - d0001_Rev1.00
The I2Cn_STATE register can be used to determine which state the I
at a given time. The register consists of the STATE bit-field, which shows which state the I
at in any ongoing transmission, and a set of single-bits, which reveal the transmission mode, whether
the bus is busy or idle, and whether the bus is held by this I
The possible values of the STATE field are summarized in Table 15.6 (p. 155) . When this field is
cleared, the I
I2Cn_STATE register are listed in Table 15.7 (p. 155) .
Table 15.6. I
Table 15.7. I
Note
The I
be addressed as an I
in a mixed mode, both capable of starting transmissions as a master, and being addressed as a slave.
I2Cn_STATE Description
-
Mode
IDLE
WAIT
START
ADDR
ADDRACK
DATA
DATAACK
Bit
BUSY
MASTER
TRANSMITTER
BUSHOLD
NACK
2
C module operates in master mode by default. To enable slave operation, i.e. to allow the device to
I2Cn_STATE reflects the internal state of the I
as long as the bus is held, i.e. as long as BUSHOLD in I2Cn_STATUS is set.
Arbitration lost
2
2
2
C STATE Values
C Transmission Status
C module is not a part of any ongoing transmission. The remaining status bits in the
Value
0
1
2
3
4
5
6
2
C slave, the SLAVE bit in I2Cn_CTRL must be set. In this case the slave operates
I2Cn_IF
ARBLOST interrupt
flag
Description
No transmission is being performed by this module.
Waiting for idle. Will send a start condition as soon as the bus is idle.
Start being transmitted
Address being transmitted or has been received
Address ACK/NACK being transmitted or received
Data being transmitted or received
Data ACK/NACK being transmitted or received
Description
Set whenever there is activity on the bus. Whether or not this module is
responsible for the activity cannot be determined by this byte.
Set when operating as a master. Cleared at all other times.
Set when operating as a transmitter; either a master transmitter or a slave
transmitter. Cleared at all other times
Set when the bus is held by this I
software.
Only valid when bus is held and STATE is ADDRACK or DATAACK. In that case
it is set if a NACK was received. In all other cases, the bit is cleared.
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155
Required
interaction
START
None
START
2
C module, and therefore only held constant
2
C module waiting for a software response.
2
Response
START will be sent when bus becomes idle
START will be sent when bus becomes idle
C module because an action is required by
2
C module and the I2C bus are in
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2
C module is