EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 160

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.3.11 Using 10-bit Addresses
15.3.12 Error Handling
15.3.12.1 ABORT command
15.3.12.2 Bus Reset
15.3.12.3 I
15.3.12.4 Bus Lockup
2010-09-06 - d0001_Rev1.00
When using 10-bit addresses in slave mode, set the I2Cn_SADDR register to 1111 0XX where XX
are the two most significant bits of the 10-bit address, and set I2Cn_SADDRMASK to 0xFF. Address
matches will now be given on all 10-bit addresses where the two most significant bits are correct.
When receiving an address match, the slave must acknowledge the address and receive the first data
byte. This byte contains the second part of the 10-bit address. If it matches the address of the slave,
the slave should ACK the byte to continue the transmission, and if it does not match, the slave should
NACK it.
When the master is operating as a master transmitter, the data bytes will follow after the second address
byte. When the master is operating as a master receiver however, a repeated START condition is sent
after the second address byte. The address sent after this repeated START is equal to the first of the
address bytes transmitted previously, but now with the R/W byte set, and only the slave that found a
match on the entire 10-bit address in the previous message should ACK this address. The repeated
start should take the master into a master receiver mode, and after the single address byte sent this
time around, the slave begins transmission to the master.
Some bus errors may require software intervention to be resolved. The I
command, which can be set in I2Cn_CMD, to help resolve bus errors.
When the bus for some reason is locked up and the I
cannot get out of, or for some other reason the I
can be used.
Setting the ABORT command will make the I
or received, release the SDA and SCL lines and go to an idle mode. ABORT effectively makes the I
module forget about any ongoing transfers.
A bus reset can be performed by setting the START and STOP commands in I2Cn_CMD while the
transmit buffer is empty. A START condition will then be transmitted, immediately followed by a STOP
condition. A bus reset can also be performed by transmitting a START command with the transmit buffer
empty and AUTOSE set.
An I
on SDA changes while SCL is high during bit-transmission on the I
the current transmission when a bus error occurs, any data currently being transmitted or received is
discarded, SDA and SCL are released, the BUSERR interrupt flag in I2Cn_IF is set to indicate the error,
and the module automatically takes a course of action as defined in Table 15.10 (p. 160) .
Table 15.10. I
A lockup occurs when a master or slave on the I
preventing other devices from putting high values on the bus, and thus making communication on the
bus impossible.
2
C-bus error occurs when a START or STOP condition is misplaced, which happens when the value
In a master/slave operation
2
C-Bus Errors
2
C Bus Error Response
Misplaced START
Treated as START. Receive address.
2
C module discard any data currently being transmitted
2
...the world's most energy friendly microcontrollers
C wants to abort a transmission, the ABORT command
160
2
C-bus has locked the SDA or SCL at a low value,
2
C module is in the middle of a transmission it
2
C-bus. If the I
Misplaced STOP
Go idle. Perform any pending actions.
2
C module provides an ABORT
www.energymicro.com
2
C module is part of
2
C