EFM32G200F16 Energy Micro, EFM32G200F16 Datasheet - Page 28

• Manufacturer Part Number: EFM32G200F16
• Description: MCU 32BIT 16KB FLASH 32-QFN
• Manufacturer: Energy Micro
• Series: Geckor

Specifications of EFM32G200F16

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: EBI/EMI, I²C, IrDA, SmartCard, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.8 V
• Data Converters: A/D 4x12b, D/A 1x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad
• Processor Series: EFM32G200
• Core: ARM Cortex-M3
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 2
• Operating Supply Voltage: 1.8 V to 3.8 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3 Functional Description
2010-09-06 - d0001_Rev1.00
• Command and status interface
• Security features
• End-of-write and end-of-erase interrupts
The size of the main block is device dependent. The largest size available is 128 KB (256 pages). The
information block is fixed in size for all devices with 512 bytes available for user data. The information
block also contains chip configuration data located in a reserved area. The main block is mapped to
address 0x00000000 and the information block is mapped to address 0x0FE00000. Table 7.1 (p. 28)
outlines how the Flash is mapped in the memory space. All Flash memory is organized into 512 byte
pages.
Table 7.1. MSC Flash Memory Mapping
1
Block/page erased by a device erase
Block
Main
Reserved
Information
Reserved
• DMA read support in EM0 and EM1
• Flash write and erase
• Core clock independent Flash timing
• Configurable interrupt erase abort
• Memory and bus fault control
• Lockable debug access
• Page lock bits
• Accessible from Cortex-M3 in EM0
• DMA write support in EM0 and EM1
• Internal oscillator and internal timers for precise and autonomous Flash timing
• Improved interrupt predictability
1
• Conditional branch target prefetch suppression
• Cortex-M3 disfolding of if-then (IT) blocks
• General purpose timers are not occupied during Flash erase and write operations
• Need for special time scaling registers eliminated
Page
0
.
255
-
0
-
1
-
2
-
-
Base address
0x00000000
0x0001FF00
0x00020000
0x0FE00000
0x0FE00200
0x0FE04000
0x0FE04200
0x0FE08000
0x0FE08200
0x0FE10000
Write/Erase by
Software, debug Yes
Software, debug Yes
Software, debug Yes
-
Software, debug Yes
-
Debug only
-
-
-
-
...the world's most energy friendly microcontrollers
28
Software
readable
-
-
Yes
-
Yes
-
-
Purpose/Name
User code and data
Reserved for flash
expansion
User Data (UD)
Reserved
Lock Bits (LB)
Reserved
Device Information
(DI)
Reserved
Reserved for flash
expansion
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Size
16 KB - 128
KB
~24 MB
2 KB/64 KB
Rest of code
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