UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 10

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

CHAPTER 4
CHAPTER 5 PORT FUNCTIONS ......................................................................................................... 102
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 140
10
3.4 Operand Address Addressing .................................................................................................... 82
4.1 Memory Bank ................................................................................................................................ 91
4.2 Difference in Representation of Memory Space ....................................................................... 92
4.3 Memory Bank Select Register (BANK) ....................................................................................... 93
4.4 Selecting Memory Bank............................................................................................................... 94
5.1 Port Functions ............................................................................................................................ 102
5.2 Port Configuration...................................................................................................................... 104
5.3 Registers Controlling Port Function ........................................................................................ 130
5.4 Port Function Operations .......................................................................................................... 135
5.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 136
5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 139
6.1 Functions of Clock Generator................................................................................................... 140
3.3.2 Immediate addressing..................................................................................................................... 80
3.3.3 Table indirect addressing ................................................................................................................ 81
3.3.4 Register addressing ........................................................................................................................ 82
3.4.1 Implied addressing .......................................................................................................................... 82
3.4.2 Register addressing ........................................................................................................................ 83
3.4.3 Direct addressing ............................................................................................................................ 84
3.4.4 Short direct addressing ................................................................................................................... 85
3.4.5 Special function register (SFR) addressing ..................................................................................... 86
3.4.6 Register indirect addressing............................................................................................................ 87
3.4.7 Based addressing ........................................................................................................................... 88
3.4.8 Based indexed addressing.............................................................................................................. 89
3.4.9 Stack addressing............................................................................................................................. 90
4.4.1 Referencing values between memory banks................................................................................... 94
4.4.2 Branching instruction between memory banks................................................................................ 96
4.4.3 Subroutine call between memory banks ......................................................................................... 98
4.4.4 Instruction branch to bank area by interrupt ...................................................................................100
5.2.1 Port 0 .............................................................................................................................................105
5.2.2 Port 1 .............................................................................................................................................111
5.2.3 Port 2 .............................................................................................................................................116
5.2.4 Port 3 .............................................................................................................................................117
5.2.5 Port 4 .............................................................................................................................................120
5.2.6 Port 5 .............................................................................................................................................121
5.2.7 Port 6 .............................................................................................................................................122
5.2.8 Port 7 .............................................................................................................................................124
5.2.9 Port 12 ...........................................................................................................................................125
5.2.10 Port 13 .........................................................................................................................................128
5.2.11 Port 14 .........................................................................................................................................129
5.4.1 Writing to I/O port ...........................................................................................................................135
5.4.2 Reading from I/O port.....................................................................................................................135
5.4.3 Operations on I/O port....................................................................................................................135
MEMORY BANK SELECT FUNCTION (
ONLY) ............................................................................................................................... 91
User’s Manual U17260EJ6V0UD
µ
PD78F0536, 78F0537, AND 78F0537D