UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 550

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(3) Port mode register 12 (PM12)
24.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
(2) Used as interrupt (LVIMD = 0)
pin is more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0
of LVIM).
550
The low-voltage detector can be used in the following two modes.
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this
time, the output latch of P120 may be 0 or 1.
PM12 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM12 to FFH.
signal when V
V (TYP.)), generates an internal reset signal when EXLVI < V
V
V
V (TYP.)). When EXLVI drops lower than V
(EXLVI ≥ V
Address: FF2CH
Symbol
EXLVI
LVI
PM12
(V
.
DD
LVISEL: Bit 2 of LVIM
< V
EXLVI
PM12n
LVI
DD
7
1
) or when V
0
1
), generates an interrupt signal (INTLVI).
< V
After reset: FFH
LVI
, and releases internal reset when V
Output mode (output buffer on)
Input mode (output buffer off)
Figure 24-4. Format of Port Mode Register 12 (PM12)
6
1
DD
becomes V
CHAPTER 24 LOW-VOLTAGE DETECTOR
R/W
5
1
User’s Manual U17260EJ6V0UD
LVI
or higher (V
P12n pin I/O mode selection (n = 0 to 4)
EXLVI
PM124
DD
DD
4
) and detection voltage (V
(EXLVI < V
) and detection voltage (V
DD
≥ V
DD
PM123
≥ V
3
LVI
EXLVI
EXLVI
), generates an interrupt signal (INTLVI).
LVI
, and releases internal reset when EXLVI ≥
) or when EXLVI becomes V
.
PM122
2
LVI
LVI
). When V
), generates an internal reset
PM121
1
DD
PM120
drops lower than
0
EXLVI
EXLVI
EXLVI
or higher
= 1.21
= 1.21