UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 170

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
170
Status Transition
(B) → (C) (X1 clock: 1 MHz ≤ f
(B) → (C) (external main clock: 1 MHz ≤ f
10 MHz)
(B) → (C) (X1 clock: 10 MHz < f
(B) → (C) (external main clock: 10 MHz < f
20 MHz)
Status Transition
(B) → (D) (XT1 clock)
(B) → (D) (external subsystem clock)
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
already been set.
CHAPTER 29
ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: T
2. EXCLK, OSCSEL, EXCLKS, OSCSELS, AMPH:
(Setting sequence of SFR registers)
(Setting sequence of SFR registers)
MSTOP:
XSEL, MCM0:
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×:
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (2/4)
Setting Flag of SFR Register
Setting Flag of SFR Register
XH
XH
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 32
≤ 10 MHz)
≤ 20 MHz)
Bits 7 to 4 and 0 of the clock operation mode select register (OSCCTL)
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Don’t care
XH
XH
≤
≤
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17260EJ6V0UD
AMPH
Unnecessary if these registers
XTSTART
0
0
1
1
0
1
0
Note
are already set
Unnecessary if the CPU is operating
EXCLK
0
1
0
1
with the subsystem clock
EXCLKS
0
×
1
OSCSEL
1
1
1
1
A
= −40 to +125°C)).
OSCSELS
MSTOP
with the high-speed
Unnecessary if the
CPU is operating
0
0
0
system clock
1
×
1
0
Must not be
Must not be
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Unnecessary
Stabilization
Waiting for
Necessary
Oscillation
XSEL
1
1
1
1
Note
CSS
MCM0
1
1
1
1
1
1