UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 395
UPD78F0537DGA(T)-9EV-A
Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0537DGA(T)-9EV-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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(2) Serial I/O shift register 1n (SIO1n)
This is an 8-bit register that converts data from parallel data into serial data and vice versa.
This register can be read by an 8-bit memory manipulation instruction.
Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n)
is 0.
During reception, the data is read from the serial input pin (SI1n) to SIO1n.
Reset signal generation sets this register to 00H.
Cautions 1. Do not access SIO1n when CSOT1n = 1 (during serial communication).
Remark n = 0:
n = 0, 1:
2. In the slave mode, reception is started when data is read from SIO11 with a low level input
to the SSI11 pin. For details on the reception operation, see 16.4.2 (2) Communication
operation.
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
User’s Manual U17260EJ6V0UD
395
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