UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 769

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

5th edition
Edition
Deletion of Caution 3 in the previous edition from figure 13-8 Format of Analog
Input Channel Specification Register (ADS)
Deletion of Caution 2 in the previous edition from figure 13-9 Format of A/D Port
Configuration Register (ADS)
Change of setting of digital input and output in Table 13-3 Setting Functions of
ANI0/P20 to ANI7/P27 Pins
Addition of (iii) Setting range when CR00n or CR01n is used as a compare
register
Partial change of description of bits 3 and 2 in Figure 7-6 Format of 16-Bit Timer
Mode Control Register 00 (TMC00) and Figure 7-7 Format of 16-Bit Timer Mode
Control Register 01 (TMC01)
Change of maximum transfer rate in 15.1 Functions of Serial Interface UART6
Change of output clock selection range and Remark 2 in Figure 15-9 Format of
Baud Rate Generator Control Register 6 (BRGC6)
Partial change of description in 15.4.3 (2) Generation of serial clock
Addition of data to be set where target baud rate is 625000 bps to and change of
Remark in Table 15-5 Set Data of Baud Rate Generator
Addition of error if division ratio (k) is 4 to Table 15-6 Maximum/Minimum
Permissible Baud Rate Error
Partial change of condition in which STCEN bit is cleared in Figure 17-7 Format of
IIC Flag Register 0 (IICF0)
Addition of descriptions (1) Master operation in single master system, (2) Master
operation in multimaster system, and (3) Slave operation to 17.5.16
Communication operations
Partial change of Figure 17-23 Master Operation in Single-Master System
Partial change of Figure 17-25 Slave Operation Flowchart (1)
Addition of Note 4 to Table 19-1 Interrupt Source List
Addition of Note 1, 2, and 4 to 6 to Table 19-2 Flags Corresponding to Interrupt
Request Sources (2/2)
Addition of oscillation accuracy stabilization time to and change of reset processing
time in Figure 21-4 HALT Mode Release by Reset
Addition of Note 1 to and change of description of Serial interface IIC0 in Table 21-3
Operating Statuses in STOP Mode
Change of Caution 4 in 21.2.2 (1) STOP mode setting and operating statuses
Change of Figure 21-5 Operation Timing When STOP Mode Is Released
Change of Figure 21-6 STOP Mode Release by Interrupt Request Generation
Addition of oscillation accuracy stabilization time to and change of reset processing
time in Figure 21-7 STOP Mode Release by Reset
Addition of oscillation accuracy stabilization time to Figures 22-2 Timing of Reset
by RESET Input to 22-4 Timing of Reset in STOP Mode by RESET Input, change
of reset processing time
Addition of Note 4 to Table 22-2. Hardware Statuses After Reset
Acknowledgment
Partial change of description in 23.1 Functions of Power-on-Clear Circuit and 23.3
Operation of Power-on-Clear Circuit
Change of voltage stabilization wait time and reset processing time in and addition of
oscillation accuracy stabilization wait time and Note 3 to (1) In 1.59 V POC mode
(option byte: POCMODE = 0) in Figure 23-2 Timing of Generation of Internal
Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
Description
CHAPTER 13 A/D
CONVERTER
CHAPTER 14 SERIAL
INTERFACE UART0
CHAPTER 15 SERIAL
INTERFACE UART6
CHAPTER 17 SERIAL
INTERFACE IIC0
CHAPTER 19
INTERRUPT
FUNCTIONS
CHAPTER 21
STANDBY FUNCTION
CHAPTER 22 RESET
FUNCTION
CHAPTER 23 POWER-
ON-CLEAR CIRCUIT
Chapter
(13/16)
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