UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 734

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

734
16-bit
timer/event
counters
00, 01
8-bit
timer/event
counters
50, 51
8-bit timers
H0, H1
Function
Sampling clock for
eliminating noise
TI00n/TI01n
CR5n: 8-bit timer
compare register 5n
TCL50: Timer clock
selection register 50 Be sure to clear bits 3 to 7 to “0”.
TCL51: Timer clock
selection register 51 Be sure to clear bits 3 to 7 to “0”.
TMC51: 8-bit timer
mode control register
51 (TMC51)
Interval timer
Square-wave output Do not write other values to CR5n during operation.
PWM output
Timer start error
CMP0n: 8-bit timer H
comparer register 0n
(CMP0n)
CMP1n: 8-bit timer H
compare register 1n
(CMP1n)
TMHMD0: 8-bit timer
H mode register 0
Details of Function
The sampling clock for eliminating noise differs depending on whether the valid
edge of TI00n is used as the count clock or capture trigger. In the former case,
the sampling clock is fixed to f
PRM0n is used for sampling.
When the signal input to the TI00n pin is sampled and the valid level is
detected two times in a row, the valid edge is detected. Therefore, noise
having a short pulse width can be eliminated (see Figure 7-9).
The signal input to the TI00n/TI01n pin is not acknowledged while the timer is
stopped, regardless of the operation mode of the CPU.
In the mode in which clear & start occurs on a match of TM5n and CR5n
(TMC5n6 = 0), do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock
(clock selected by TCL5n) or more.
When rewriting TCL50 to other data, stop the timer operation beforehand.
When rewriting TCL51 to other data, stop the timer operation beforehand.
The settings of LVS5n and LVR5n are valid in other than PWM mode.
Perform <1> to <4> below in the following order, not at the same time.
<1> Set TMC5n1, TMC5n6:
<2> Set TOE5n to enable output:
<3> Set LVS5n, LVR5n (see Caution 1): Timer F/F setting
<4> Set TCE5n
When TCE5n = 1, setting the other bits of TMC5n is prohibited.
The actual TO50/TI50/P17 and TO51/TI51/P33/INTP4 pin outputs are
determined depending on PM17 and P17, and PM33 and P33, besides TO5n
output.
Do not write other values to CR5n during operation.
In PWM mode, make the CR5n rewrite period 3 count clocks of the count clock
(clock selected by TCL5n) or more.
When reading from CR5n between <1> and <2> in Figure 8-15, the value read
differs from the actual value (read value: M, actual value of CR5n: N).
An error of up to one clock may occur in the time required for a match signal to
be generated after timer start. This is because 8-bit timer counters 50 and 51
(TM50, TM51) are started asynchronously to the count clock.
CMP0n cannot be rewritten during timer count operation. CMP0n can be
refreshed (the same value is written) during timer count operation.
In the PWM output mode and carrier generator mode, be sure to set CMP1n
when starting the timer count operation (TMHEn = 1) after the timer count
operation was stopped (TMHEn = 0) (be sure to set again even if setting the
same value to CMP1n).
When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However,
TMHMD0 can be refreshed (the same value is written).
In the PWM output mode, be sure to set the 8-bit timer H compare register 10
(CMP10) when starting the timer count operation (TMHE0 = 1) after the timer
count operation was stopped (TMHE0 = 0) (be sure to set again even if setting
the same value to CMP10).
The actual TOH0/P15 pin output is determined depending on PM15 and P15,
besides TOH0 output.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
PRS
. In the latter, the count clock selected by
Cautions
Operation mode setting
Timer output enable
p. 250
p. 250
p. 253
p. 253
p. 254
p. 254
p. 255
p. 255
p. 257
p. 257
p. 257
p. 257
p. 259
p. 262
p. 263
p. 266
p. 267
p. 271
p. 271
p. 274
p. 274
p. 274
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