UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 449

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

17.5.15 Other cautions
(1) When STCEN (bit 1 of IIC flag register 0 (IICF0)) = 0
(2) When STCEN = 1
(3) If other I
(4) Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1, and 0 of IICL0), and CLX0
Immediately after I
1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition
has been detected to a master device communication mode, first generate a stop condition to release the bus,
then perform master device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for generating a stop condition.
<1> Set IIC clock selection register 0 (IICCL0).
<2> Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
<3> Set bit 0 (SPT0) of IICC0 to 1.
Immediately after I
regardless of the actual bus status. To generate the first start condition (STT0 (bit 1 of IIC control register 0
(IICC0)) = 1), it is necessary to confirm that the bus has been released, so as to not disturb other
communications.
If I
pin is low and the SCL0 pin is high, the macro of I
start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned,
but this interferes with other I
<1> Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request signal (INTIIC0) when the
<2> Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after setting IICE0 to 1), to forcibly
(bit 0 of IICX0) before enabling the operation (IICE0 = 1). To change the transfer clock frequency, clear
IICE0 to 0 once.
2
C operation is enabled and the device participates in communication already in progress when the SDA0
stop condition is detected.
disable detection.
2
C communications are already in progress
2
C operation is enabled (IICE0 = 1), the bus communication status (IICBSY (bit 6 of IICF0) =
2
C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
2
C communications. To avoid this, start I
CHAPTER 17 SERIAL INTERFACE IIC0
CL01
0
0
1
1
Table 17-7. Wait Periods
User’s Manual U17260EJ6V0UD
CL00
0
1
0
1
2
C recognizes that the SDA0 pin has gone low (detects a
6 clocks
6 clocks
12 clocks
3 clocks
Wait Period
2
C.
2
C in the following sequence.
449