UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 281

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
<R>
9.4.2 Operation as PWM output
register during timer operation is prohibited.
register during timer operation is possible.
counter Hn and the CMP0n register match after the timer count is started. PWM output (TOHn output) outputs an
inactive level when 8-bit timer counter Hn and the CMP1n register match.
TMHMDn
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n
The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n
The operation in PWM output mode is as follows.
PWM output (TOHn output) outputs an active level and 8-bit timer counter Hn is cleared to 0 when 8-bit timer
<1> Set each register.
<2> The count operation starts when TMHEn = 1.
<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.
<4> When the 8-bit timer counter Hn and the CMP1n register match, an inactive level is output and the compare
Setting
(i) Setting timer H mode register n (TMHMDn)
(ii) Setting CMP0n register
(iii) Setting CMP1n register
When the values of the 8-bit timer counter Hn and the CMP0n register match, the 8-bit timer counter Hn is
cleared, an interrupt request signal (INTTMHn) is generated, and an active level is output. At the same time,
the compare register to be compared with the 8-bit timer counter Hn is changed from the CMP0n register to
the CMP1n register.
register to be compared with the 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n
register. At this time, the 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.
TMHEn
• Compare value (N): Cycle setting
• Compare value (M): Duty setting
0
Remarks 1. n = 0, 1
CKSn2
0/1
2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
CKSn1
Figure 9-11. Register Setting in PWM Output Mode
0/1
CHAPTER 9 8-BIT TIMERS H0 AND H1
CKSn0
0/1
User’s Manual U17260EJ6V0UD
TMMDn1
1
TMMDn0 TOLEVn
0
0/1
TOENn
1
Timer output enabled
Default setting of timer output level
PWM output mode selection
Count clock (f
Count operation stopped
CNT
) selection
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