UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 597

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

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27.1 Connecting QB-78K0MINI or QB-MINI2 to
V
OCD0A/X1 and OCD1A/P31, or OCD0B/X2 and OCD1B/P32 are used can be selected.
SS
The
Caution The
Notes 1. This connection is designed assuming that the reset signal is output from the N-ch open-drain buffer
Cautions 1. Input the clock from the OCD0A/X1 pin during on-chip debugging.
pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI or QB-MINI2). Whether
µ
PD78F0537D uses the V
2. Make pull-down resistor 470 Ω or more (10 kΩ: recommended).
3. Characters without parentheses represent the QB-78K0MINI name, and those within parenthesis the
2. Control the OCD0A/X1 and OCD0B/X2 pins by externally pulling down the OCD1A/P31 pin or
because its reliability cannot be guaranteed after the on-chip debug function has been used,
given the issue of the number of times the flash memory can be rewritten. NEC Electronics does
not accept complaints concerning this product.
(output resistance: 100 Ω or less). For details, refer to QB-78K0MINI User’s Manual (U17029E) or QB-
MINI2 User’s Manual (U18371E).
QB-MINI2 name.
Figure 27-1. Connection Example of QB-78K0MINI or QB-MINI2 and
by using an external circuit using the P130 pin (that outputs a low level when the device is
reset).
Target connector
(10-pin)
CHAPTER 27 ON-CHIP DEBUG FUNCTION (
µ
PD78F0537D has an on-chip debug function. Do not use this product for mass production
X2 (DATA)
RESET_IN
RESET_OUT
X1 (CLK)
FLMD0
R.F.U.
R.F.U.
GND
GND
Note 3
Note 3
V
Note 1
DD
DD
(Open)
(Open)
(When OCD0A/X1 and OCD0B/X2 Are Used)
, FLMD0, RESET, OCD0A/X1 (or OCD1A/P31), OCD0B/X2 (or OCD1B/P32), and
V
DD
(Recommended)
User’s Manual U17260EJ6V0UD
10 kΩ
Note 2
µ
PD78F0537D
V
Note 2
DD
1 kΩ
(Recommended)
µ
V
DD
PD78F0537D ONLY)
Reset circuit
X2/OCD0B
GND
Reset signal
Target device
V
X1/OCD0A
P31
RESET
FLMD0
DD
µ
PD78F0537D
597