UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 240

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(3) Measuring the pulse width by using one input signal of the TI00n pin (clear & start mode entered by the
240
Capture & count clear input
<1> Pulse cycle =
<2> High-level pulse width = (10000H × Number of times OVF0n bit is set to 1 + Captured value of CR00n) ×
<3> Low-level pulse width = (Pulse cycle − High-level pulse width)
TI00n pin valid edge input)
Set the clear & start mode entered by the TI00n pin valid edge (TMC0n3 and TMC0n2 = 10). The count value of
TM0n is captured to CR00n in the phase reverse to the valid edge of the TI00n pin, and the count value of TM0n
is captured to CR01n and TM0n is cleared (0000H) when the valid edge of the TI00n pin is detected. Therefore,
a cycle is stored in CR01n if TM0n does not overflow.
If an overflow occurs, take the value that results from adding 10000H to the value stored in CR01n as a cycle.
Clear bit 0 (OVF0n) of 16-bit timer mode control register 0n (TMC0n) to 0.
Remark n = 0:
Capture trigger input
(TMC0n3, TMC0n2)
Capture interrupt
Capture interrupt
Capture register
Capture register
TM0n register
n = 0, 1:
Operable bits
Overflow flag
(INTTM01n)
(INTTM00n)
(CR00n)
(CR01n)
(OVF0n)
(TI00n)
(TI01n)
FFFFH
0000H
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Figure 7-55. Timing Example of Pulse Width Measurement (3)
00
L
L
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
0000H
0000H
• TMC0n = 08H, PRM0n = 10H, CRC0n = 07H
(10000H × Number of times OVF0n bit is set to 1 + Captured value of CR01n) ×
Count clock cycle
Count clock cycle
10
M
<2>
A
User’s Manual U17260EJ6V0UD
M
<1>
<3>
N
A
<2>
<1>
N
B
<3>
S
0 write clear
B
<2>
<1>
S
C
<3>
P
C
<2>
<1>
P
D
<3>
Q
D
Q
00