UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 411

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
The first bit is directly latched by the SOTB1n register at the falling edge of the write signal of the SOTB1n
register or the read signal of the SIO1n register, and output from the SO1n pin via an output selector. Then, the
value of the SOTB1n register is transferred to the SIO1n register at the next falling (or rising) edge of SCK1n, and
shifted one bit. At the same time, the first bit of the receive data is stored in the SIO1n register via the SI1n pin.
The second and subsequent bits are latched by the SIO1n register to the output latch at the next rising (or falling)
edge of SCK1n, and the data is output from the SO1n pin.
Remark n = 0:
n = 0, 1:
Writing to SOTB1n or
Writing to SOTB1n or
reading from SIO1n
reading from SIO1n
Output latch
Output latch
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
SOTB1n
SOTB1n
SCK1n
SCK1n
SIO1n
SIO1n
SO1n
SO1n
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
Figure 16-11. Output Operation of First Bit (2/2)
(d) Type 4: CKP1n = 1, DAP1n = 1
(c) Type 2: CKP1n = 0, DAP1n = 1
User’s Manual U17260EJ6V0UD
First bit
First bit
2nd bit
2nd bit
3rd bit
3rd bit
411

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