UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 428

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

428
(3) IIC flag register 0 (IICF0)
Condition for clearing (ACKD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (STD0 = 0)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock following
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
Condition for clearing (SPD0 = 0)
• At the rising edge of the address transfer byte’s first
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
ACKD0
address transfer
clock following setting of this bit and detection of a start
condition
STD0
SPD0
Remark
This register sets the operation mode of I
IICF0 is set by a 1-bit or 8-bit memory manipulation instruction. However, the STCF and IICBSY bits are read-
only.
The IICRSV bit can be used to enable/disable the communication reservation function (see 17.5.14
Communication reservation).
STCEN can be used to set the initial value of the IICBSY bit (see 17.5.15 Other cautions).
IICRSV and STCEN can be written only when the operation of I
register 0 (IICC0) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation sets IICF0 to 00H.
0
1
0
1
0
1
Acknowledge was not detected.
Acknowledge was detected.
Start condition was not detected.
Start condition was detected. This indicates that the address transfer period is in effect.
Stop condition was not detected.
Stop condition was detected. The master device’s communication is terminated and the bus is released.
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Bit 7 of IIC control register 0 (IICC0)
Figure 17-6. Format of IIC Status Register 0 (IICS0) (3/3)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17260EJ6V0UD
2
C and indicates the status of the I
Detection of acknowledge (ACK)
Detection of start condition
Detection of stop condition
Condition for setting (ACKD0 = 1)
• After the SDA0 line is set to low level at the rising edge of
Condition for setting (STD0 = 1)
• When a start condition is detected
Condition for setting (SPD0 = 1)
• When a stop condition is detected
SCL0’s ninth clock
2
C is disabled (bit 7 (IICE0) of IIC control
2
C bus.