UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 764

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
764
3rd edition
Edition
Modification of Figure 17-27 Example of Master to Slave Communication (When
9-Clock Wait Is Selected for Both Master and Slave) and Figure 17-28 Example
of Slave to Master Communication (When 8-Clock Wait Is Selected for Master, 9-
Clock Wait Is Selected for Slave)
Modification of Figure 18-7. Timing Chart of Division Operation (DCBA2586H ÷
0018H)
Modification of Caution 3 in 21.1.1 Standby function
Modification of description in 21.1.2 (2) Oscillation stabilization time select
register (OSTS)
Addition of clock output and buzzer output to items in and addition of Note to Table
21-1 Operating Statuses in HALT Mode
Modification of Figure 21-4 HALT Mode Release by Reset
Addition of clock output and buzzer output to items in and addition of Note to Table
21-3 Operating Statuses in STOP Mode
Modification of Figure 21-5 Operation Timing When STOP Mode Is Released
Modification of Figure 21-7 STOP Mode Release by Reset
Addition of description when (i) When WTIM0 = 0 to the following items in 17.5.17 (6)
Operation when arbitration loss occurs (no communication after arbitration
loss)
(f) When arbitration loss occurs due to low-level data when attempting to
(g) When arbitration loss occurs due to a stop condition when attempting to
Modification of the value of the following items of IICS0 register in 17.5.17
(2) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not
extension code))
(2) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not
extension code))
(3) (d) (i) When WTIM0 = 0 (after restart, does not match with address (= not
extension code))
(3) (d) (ii) When WTIM0 = 1 (after restart, does not match with address (= not
extension code))
(6) (d) (ii) Extension code
(6) (e) When loss occurs due to stop condition during data transfer
(6) (h) (ii) When WTIM0 = 1
Addition of description to 17.5.17 (5) Arbitration loss operation (operation as
slave after arbitration loss) and (6) Operation when arbitration loss occurs (no
communication after arbitration loss)
(h) When arbitration loss occurs due to low-level data when attempting to
generate a stop condition
generate a restart condition
generate a restart condition
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
Description
CHAPTER 17 SERIAL
INTERFACE IIC0
CHAPTER 18
MULTIPLIER/DIVIDER
(
78F0535, 78F0536,
78F0537, AND
78F0537D ONLY)
CHAPTER 21
STANDBY FUNCTION
µ
PD78F0534,
Chapter
(8/16)

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