UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 735

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

8-bit
timers H0,
H1
Watch
timer
Function
TMHMD1: 8-bit
timer H mode
register 1
TMCYC1: 8-bit
timer H carrier
register 1
PWM output
Carrier
generator (8-bit
timer H1 only)
WTM: Watch
timer operation
mode register
Interrupt
request
Details of
Function
When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However,
TMHMD1 can be refreshed (the same value is written).
In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H
compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1)
after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even
if setting the same value to CMP11).
When the carrier generator mode is used, set so that the count clock frequency of
TMH1 becomes more than 6 times the count clock frequency of TM51.
The actual TOH1/INTP5/P16 pin output is determined depending on PM16 and P16,
besides TOH1 output.
Do not rewrite RMC1 when TMHE = 1. However, TMCYC1 can be refreshed (the
same value is written).
The set value of the CMP1n register can be changed while the timer counter is
operating. However, this takes a duration of three operating clocks (signal selected
by the CKSn2 to CKSn0 bits of the TMHMDn register) from when the value of the
CMP1n register is changed until the value is transferred to the register.
Be sure to set the CMP1n register when starting the timer count operation (TMHEn =
1) after the timer count operation was stopped (TMHEn = 0) (be sure to set again
even if setting the same value to the CMP1n register).
Make sure that the CMP1n register setting value (M) and CMP0n register setting
value (N) are within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Do not rewrite the NRZB1 bit again until at least the second clock after it has been
rewritten, or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.
When the 8-bit timer/event counter 51 is used in the carrier generator mode, an
interrupt is generated at the timing of <1>. When the 8-bit timer/event counter 51 is
used in a mode other than the carrier generator mode, the timing of the interrupt
generation differs.
Be sure to set the CMP11 register when starting the timer count operation (TMHE1 =
1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again
even if setting the same value to the CMP11 register).
Set so that the count clock frequency of TMH1 becomes more than 6 times the count
clock frequency of TM51.
Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.
The set value of the CMP11 register can be changed while the timer counter is
operating. However, it takes the duration of three operating clocks (signal selected
by the CKS12 to CKS10 bits of the TMHMD1 register) since the value of the CMP11
register has been changed until the value is transferred to the register.
Be sure to set the RMC1 bit before the count operation is started.
Do not change the count clock and interval time (by setting bits 4 to 7 (WTM4 to
WTM7) of WTM) during watch timer operation.
When operation of the watch timer and 5-bit counter is enabled by the watch timer
mode control register (WTM) (by setting bits 0 (WTM0) and 1 (WTM1) of WTM to 1),
the interval until the first interrupt request signal (INTWT) is generated after the
register is set does not exactly match the specification made with bits 2 and 3
(WTM2, WTM3) of WTM. Subsequently, however, the INTWT signal is generated at
the specified intervals.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
Cautions
p. 276
p. 276
p. 276
p. 276
p. 276
p. 282
p. 282
p. 282
p. 288
p. 288
p. 290
p. 290
p. 290
p. 290
p. 290
p. 297
p. 299
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