UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 148

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
(5) Main OSC control register (MOC)
148
This register selects the operation mode of the high-speed system clock.
This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the
CPU operates with a clock other than the high-speed system clock.
MOC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 80H.
Address: FFA2H
Symbol
MOC
Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
MSTOP
MSTOP
<7>
0
1
After reset: 80H
2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
3. The peripheral hardware cannot operate when the peripheral hardware clock is
Figure 6-5. Format of Main OSC Control Register (MOC)
X1 oscillator operating
X1 oscillator stopped
other than the high-speed system clock. Specifically, set under either of the
following conditions.
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
register (OSCCTL) is 0 (I/O port mode).
stopped.
peripheral hardware clock has been stopped, initialize the peripheral hardware.
6
0
R/W
X1 oscillation mode
CHAPTER 6 CLOCK GENERATOR
To resume the operation of the peripheral hardware after the
User’s Manual U17260EJ6V0UD
5
0
Control of high-speed system clock operation
4
0
3
0
External clock from EXCLK pin is enabled
External clock from EXCLK pin is disabled
External clock input mode
2
0
1
0
0
0

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