UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 196

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

7.4 Operation of 16-Bit Timer/Event Counters 00 and 01
7.4.1 Interval timer operation
mode entered upon a match between TM0n and CR00n), the count operation is started in synchronization with the
count clock.
(INTTM00n) is generated. This INTTM00n signal enables TM0n to operate as an interval timer.
196
If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to 11 (clear & start
When the value of TM0n later matches the value of CR00n, TM0n is cleared to 0000H and a match interrupt signal
Remarks 1. For the setting of I/O pins, see 7.3 (5) Port mode register 0 (PM0).
Remark n = 0:
Compare match interrupt
(TMC0n3, TMC0n2)
2. For how to enable the INTTM00n interrupt, see CHAPTER 19 INTERRUPT FUNCTIONS.
Compare register
n = 0, 1:
Count clock
TM0n register
Operable bits
(INTTM00n)
(CR00n)
TMC0n3, TMC0n2
0000H
µ
µ
Operable bits
Figure 7-17. Basic Timing Example of Interval Timer Operation
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Figure 7-16. Block Diagram of Interval Timer Operation
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
00
Interval
(N + 1)
User’s Manual U17260EJ6V0UD
N
16-bit counter (TM0n)
CR00n register
Clear
Interval
(N + 1)
N
Match signal
11
N
Interval
(N + 1)
N
INTTM00n signal
Interval
(N + 1)
N