UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 273

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
Notes 1.
2.
TMHMD0
If the peripheral hardware clock (f
f
• V
• V
• V
If the peripheral hardware clock (f
= 0), when 1.8 V ≤ V
prohibited.
Address: FF69H
PRS
DD
DD
DD
operating frequency varies depending on the supply voltage.
= 4.0 to 5.5 V: f
= 2.7 to 4.0 V: f
= 1.8 to 2.7 V: f
Figure 9-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
TMMD01
TOLEV0
TMHE0
TOEN0
TMHE0
CKS02
Other than above
<7>
0
1
0
0
0
0
1
1
0
1
0
1
0
1
Other than above
After reset: 00H
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMMD00
Low level
High level
Disables output
Enables output
PRS
PRS
PRS
DD
CKS02
CKS01
CHAPTER 9 8-BIT TIMERS H0 AND H1
0
0
0
0
1
1
0
0
< 2.7 V, the setting of CKS02 = CKS01 = CKS00 = 0 (count clock: f
6
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz (Standard and (A) grade products only)
User’s Manual U17260EJ6V0UD
Interval timer mode
PWM output mode
Setting prohibited
CKS00
CKS01
PRS
PRS
0
1
0
1
0
1
5
R/W
Timer output level control (in default mode)
) operates on the internal high-speed oscillation clock (f
) operates on the high-speed system clock (f
f
f
f
f
f
TM50 output
Setting prohibited
PRS
PRS
PRS
PRS
PRS
CKS00
Note 2
/2
/2
/2
/2
4
Timer output control
2
6
10
Timer operation enable
f
2 MHz
2 MHz
1 MHz
500 kHz
31.25 kHz
1.95 kHz
PRS
Timer operation mode
TMMD01 TMMD00 TOLEV0
Note 3
Count clock selection
=
3
f
5 MHz
5 MHz
2.5 MHz
1.25 MHz
78.13 kHz
4.88 kHz
PRS
=
2
f
10 MHz
10 MHz
5 MHz
2.5 MHz
156.25 kHz
9.77 kHz
PRS
Note 1
<1>
=
f
20 MHz
20 MHz
10 MHz
5 MHz
312.5 kHz
19.54 kHz
PRS
TOEN0
<0>
=
XH
) (XSEL = 1), the
RH
) (XSEL
PRS
273
) is