UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 453

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(2) Master operation in multi-master system
Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period
1
No
of one frame). If the SDA0 pin is constantly at low level, decide whether to release the I
SDA0 pins = high level) in conformance with the specifications of the product that is communicating.
ACKE0 = WTIM0 = SPIE0 = 1
Setting STCEN and IICRSV
Checking bus status
Enables reserving
interrupt occurs?
Master operation
communication.
IICCL0 ← XXH
SVA0 ← XXH
IICC0 ← XXH
IICX0 ← 0XH
IICF0 ← 0XH
IICRSV = 0?
Setting port
SPD0 = 1?
SPIE0 = 1
IICE0 = 1
INTIIC0
START
starts?
A
Yes
Yes
Yes
Yes
(Communication start request)
•
•
Bus status is
being checked.
Waiting to be specified as a slave by other master
Waiting for a communication start request (depends on user program)
Figure 17-24. Master Operation in Multi-Master System (1/3)
Note
Disables reserving
communication.
(No communication start request)
No
No
No
Sets each pin in the I
Selects a transfer clock.
Sets a local address.
Sets a start condition.
Releases the bus for a specific period.
Slave operation
B
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17260EJ6V0UD
STCEN = 1?
2
C mode (see 17.3 (7) Port mode register 6 (PM6)).
interrupt occurs?
Yes
Slave operation
SPIE0 = 0
INTIIC0
Yes
No
Waits for a communication request.
No
interrupt occurs?
SPD0 = 1?
SPT0 = 1
INTIIC0
Yes
Yes
No
No
Waits for detection
of the stop condition.
Prepares for starting
communication
(generates a stop condition).
Slave operation
2
C bus (SCL0 and
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