UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 506

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
Address: FF48H
Symbol
EGP
Address: FF49H
Symbol
EGN
506
These registers specify the valid edge for INTP0 to INTP7.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to 00H.
Table 19-3 shows the ports corresponding to EGPn and EGNn.
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
Remark n = 0 to 7
EGP7
EGN7
EGPn
Detection Enable Register
7
7
0
0
1
1
After reset: 00H
After reset: 00H
Figure 19-5. Format of External Interrupt Rising Edge Enable Register (EGP)
EGP0
EGP1
EGP2
EGP3
EGP4
EGP5
EGP6
EGP7
detected when the external interrupt function is switched to the port function.
EGN6
EGNn
EGP6
6
6
0
1
0
1
Table 19-3. Ports Corresponding to EGPn and EGNn
and External Interrupt Falling Edge Enable Register (EGN)
EGN0
EGN1
EGN2
EGN3
EGN4
EGN5
EGN6
EGN7
R/W
R/W
Edge detection disabled
Falling edge
Rising edge
Both rising and falling edges
EGN5
CHAPTER 19 INTERRUPT FUNCTIONS
EGP5
5
5
P120
P30
P31
P32
P33
P16
P140
P141
User’s Manual U17260EJ6V0UD
Edge Detection Port
EGN4
EGP4
INTPn pin valid edge selection (n = 0 to 7)
4
4
EGN3
EGP3
3
3
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
INTP7
EGN2
EGP2
2
2
Interrupt Request Signal
EGN1
EGP1
1
1
EGP0
EGN0
0
0