UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 736

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

736
Watchdog
timer
Clock output/
buzzer output
controller
A/D converter
Function
WDTE:
Watchdog timer
enable register
Operation
control
Setting overflow
time of
watchdog timer,
Setting window
open period of
watchdog time
Setting window
open period of
watchdog timer
CKS: clock
output select
register
ADCR: 10-bit
A/D conversion
register,
ADCRH: 8-bit
A/D conversion
register
ADM: A/D
converter mode
register
A/D conversion
timer selection
Details of
Function
If a value other than ACH is written to WDTE, an internal reset signal is
generated. If the source clock to the watchdog timer is stopped, however, an
internal reset signal is generated when the source clock to the watchdog timer
resumes operation.
If a 1-bit memory manipulation instruction is executed for WDTE, an internal
reset signal is generated. If the source clock to the watchdog timer is stopped,
however, an internal reset signal is generated when the source clock to the
watchdog timer resumes operation.
The value read from WDTE is 9AH/1AH (this differs from the written value
(ACH)).
The first writing to WDTE after a reset release clears the watchdog timer, if it is
made before the overflow time regardless of the timing of the writing, and the
watchdog timer starts counting again.
If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow
time may be different from the overflow time set by the option byte by up to 2/f
seconds.
The watchdog timer can be cleared immediately before the count value
overflows (FFFFH).
The operation of the watchdog timer in the HALT and STOP modes differs as
follows depending on the set value of bit 0 (LSROSC) of the option byte (see
Table on p. 304).
If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP
mode is released. At this time, the counter is not cleared to 0 but starts
counting from the value at which it was stopped.
If oscillation of the internal low-speed oscillator is stopped by setting LSRSTOP
(bit 1 of the internal oscillation mode register (RCM) = 1) when LSROSC = 0,
the watchdog timer stops operating. At this time, the counter is not cleared to 0.
The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 =
WINDOW0 = 0 is prohibited.
The watchdog timer continues its operation during self-programming and
EEPROM emulation of the flash memory. During processing, the interrupt
acknowledge time is delayed. Set the overflow time and window size taking this
delay into consideration.
The first writing to WDTE after a reset release clears the watchdog timer, if it is
made before the overflow time regardless of the timing of the writing, and the
watchdog timer starts counting again.
Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0). p. 310
Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).
When data is read from ADCR and ADCRH, a wait cycle is generated. Do not
read data from ADCR and ADCRH when the CPU is operating on the
subsystem clock and the peripheral hardware clock is stopped. For details, see
CHAPTER 35 CAUTIONS FOR WAIT.
A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and
LV0 to values other than the identical data.
If data is written to ADM, a wait cycle is generated. Do not write data to ADM
when the CPU is operating on the subsystem clock and the peripheral hardware
clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT.
Set the conversion times with the following conditions.
• 4.0 V ≤ AV
• 2.7 V ≤ AV
• 2.3 V ≤ AV
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
REF
REF
REF
≤ 5.5 V: f
< 4.0 V: f
< 2.7 V: f
AD
AD
AD
= 0.6 to 3.6 MHz
= 0.6 to 1.8 MHz
= 0.6 to 1.48 MHz
Cautions
RL
p. 302
p. 302
p. 302
p. 303
p. 303
p. 303
p. 304
pp. 304,
305
pp. 304,
305
p. 305
p. 310
p. 314
p. 316
p. 316
p. 317
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