UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 768

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

768
5th edition
Edition
Change of Remark in Figure 6-14 CPU Clock Status Transition Diagram (When
1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Change of CPU clock supply stop time when AMPH = 1 in Table 6-6 Changing CPU
Clock
Change of Remark 2 in Table 6-7 Time Required for Switchover of CPU Clock
and Main System Clock Cycle Division Factor
Addition of (iii) Setting range when CR00n or CR01n is used as a compare
register
Partial change of description of bits 3 and 2 in Figure 7-6 Format of 16-Bit Timer
Mode Control Register 00 (TMC00) and Figure 7-7 Format of 16-Bit Timer Mode
Control Register 01 (TMC01)
Change of (c) 16-bit timer output control register 0n (TOC0n) of Figure 7-22
Example of Register Settings for Square-Wave Output Operation
Change of timing chart in Figure 7-23 Example of Software Processing for
Square-Wave Output Function
Change of (c) 16-bit timer output control register 0n (TOC0n) of Figure 7-25
Example of Register Settings in External Event Counter Mode
Change of Figure 7-26 Example of Software Processing in External Event
Counter Mode
Change of Figure 7-40 Timing Example of Free-Running Timer Mode
(CR00n: Compare Register, CR01n: Capture Register) (change of figure to that
where CR00n = 0000H)
Change of Caution 3 in Figure 8-7 Format of 8-Bit Timer Mode Control Register
50 (TMC50) and Figure 8-8 Format of 8-Bit Timer Mode Control Register 51
(TMC51)
Change of set value of TMC5n in Setting <1> in 8.4.2 Operation as external event
counter
Change of Caution in Figure 9-3 Format of 8-bit Timer H Compare Register 0n
(CMP0n)
Partial addition of description to 9.2 (2) 8-bit timer H compare register 1n (CMP1n)
Change of Caution 1 of Figure 9-5 Format of 8-Bit Timer H Mode Register 0
(TMHMD0) and Figure 9-6 Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
Partial change of description of RMC1 and NRZB1 bits in and addition of Caution to
Figure 9-7 Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)
Change of (c) Operation when CMP0n = 00H in Figure 9-10 Timing of Interval
Timer/Square-Wave Output Operation
Partial change of description of RMC1 and NRZB1 bits in 9.4.3 (2) Carrier output
control
Change of Caution 5 in 11.4.1 Controlling operation of watchdog timer
Change of Caution 2 in Table 11-3 Setting of Overflow Time of Watchdog Timer
and
Table 11-4 Setting Window Open Period of Watchdog Timer
Change of Caution in Figure 7-46 Example of Register Settings for PPG Output
Operation
Change of Caution in Figure 7-49 Example of Register Settings for One-Shot
Pulse Output Operation
Change of restrictions on operations as external event counter, as PPG output, and
as one-shot pulse output in Table 7-5 Restrictions for Each Channel of 16-Bit
Timer/Event Counter 0n
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
Description
CHAPTER 6 CLOCK
GENERATOR
CHAPTER 7 16-BIT
TIMER/EVENT
COUNTERS 00 AND 01
CHAPTER 8 8-BIT
TIMER/EVENT
COUNTERS 50 AND 51
CHAPTER 9 8-BIT
TIMER/EVENT
COUNTERS H0 AND H1
CHAPTER 11
WATCHDOG TIMER
Chapter
(12/16)