UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 427

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Condition for clearing (TRC0 = 0)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Cleared by WREL0 = 1
• When ALD0 changes from 0 to 1 (arbitration loss)
• Reset
<Master>
• When “1” is output to the first byte’s LSB (transfer
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer direction
<When not used for communication>
Condition for clearing (COI0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
direction specification bit)
specification bit)
TRC0
Note If the wait status is canceled by setting bit 5 (WREL0) of IIC control register 0 (IICC0) to 1 at the ninth
Remark
COI0
0
1
0
1
clock when bit 3 (TRC0) of IIC status register 0 (IICS0) is 1, TRC0 is cleared, and the SDA0 line goes
into a high-impedance state.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the
falling edge of the first byte’s ninth clock).
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
Bit 7 of IIC control register 0 (IICC0)
Note
Figure 17-6. Format of IIC Status Register 0 (IICS0) (2/3)
(wait cancel)
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17260EJ6V0UD
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI0 = 1)
• When the received address matches the local address
Condition for setting (TRC0 = 1)
<Master>
• When a start condition is generated
• When “0” is output to the first byte’s LSB (transfer
<Slave>
• When “1” is input to the first byte’s LSB (transfer
(slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
direction specification bit)
direction specification bit)
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