UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 172

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
172
(B) → (E)
(C) → (F)
(D) → (G)
Status Transition
(D) → (C) (X1 clock: 1 MHz ≤ f
10 MHz)
(D) → (C) (external main clock: 1 MHz ≤
f
(D) → (C) (X1 clock: 10 MHz < f
20 MHz)
(D) → (C) (external main clock: 10 MHz <
f
(B) → (H)
(C) → (I)
XH
XH
Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14.
≤ 10 MHz
≤ 20 MHz)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence of SFR registers)
already been set.
CHAPTER 29
ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: T
2. EXCLK, OSCSEL, AMPH: Bits 7, 6 and 0 of the clock operation mode select register (OSCCTL)
Setting Flag of SFR Register
Status Transition
Status Transition
MSTOP:
XSEL, MCM0:
CSS:
Table 6-5. CPU Clock Transition and SFR Register Setting Examples (4/4)
XH
(Setting sequence)
XH
ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) to CHAPTER 32
≤
≤
Unnecessary if these registers
AMPH
CHAPTER 6 CLOCK GENERATOR
Bit 7 of the main OSC control register (MOC)
Bits 2 and 0 of the main clock mode register (MCM)
Bit 4 of the processor clock control register (PCC)
0
0
1
1
User’s Manual U17260EJ6V0UD
Note
Executing HALT instruction
Stopping peripheral functions that
cannot operate in STOP mode
are already set
EXCLK
0
1
0
1
OSCSEL
1
1
1
1
with the high-speed
MSTOP
Unnecessary if the
CPU is operating
system clock
0
0
0
0
A
= −40 to +125°C)).
Setting
Must not be
Must not be
Setting
checked
checked
Must be
Must be
Register
checked
checked
OSTC
Executing STOP instruction
XSEL
Unnecessary if this register
1
1
1
1
Note
is already set
MCM0
1
1
1
1
CSS
0
0
0
0