UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 434

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UPD78F0537DGA(T)-9EV-A

Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet

Specifications of UPD78F0537DGA(T)-9EV-A

Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
17.4 I
17.4.1 Pin configuration
resistor is required.
434
The serial clock pin (SCL0) and serial data bus pin (SDA0) are configured as follows.
(1) SCL0....... This pin is used for serial clock input and output.
(2) SDA0 ...... This pin is used for serial data input and output.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
2
C Bus Mode Functions
(Clock input)
Clock output
Data output
Data input
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Master device
V
V
SS
SS
Figure 17-11. Pin Configuration Diagram
CHAPTER 17 SERIAL INTERFACE IIC0
SCL0
SDA0
User’s Manual U17260EJ6V0UD
V
V
DD
DD
SCL0
SDA0
V
V
SS
SS
Slave device
(Clock output)
Clock input
Data output
Data input

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