UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 753

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

CHAPTER 8 8-BIT TIMER/EVENT COUNTERS 50 AND 51
Entire
chapter
p. 254
p. 255
p. 257
CHAPTER 9 8-BIT TIMERS H0 AND H1
Entire
chapter
pp. 273, 274
pp. 275, 276
p. 288
pp. 291, 292
CHAPTER 10 WATCH TIMER
p. 297
CHAPTER 11 WATCHDOG TIMER
p. 306
CHAPTER 12 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
p. 309
CHAPTER 13 A/D CONRERTER
p. 315
p. 315
p. 316
CHAPTER 14 SERIAL INTERFACE UART0
p. 336
pp. 341, 342
p. 351
CHAPTER 15 SERIAL INTERFACE UART6
p. 360
p. 366
p. 387
p. 388
Remark “Classification” in the above table classifies revisions as follows.
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
• TO50 pin output → TO50 output, TO51 pin output → TO51 output
• Addition of TO50, TO51 output in block diagram
Addition of Notes 1 and 2 to Figure 8-5 Format of Timer Clock Selection Register 50 (TCL50)
Addition of Notes 1 and 2 to Figure 8-6 Format of Timer Clock Selection Register 51 (TCL51)
Addition of Caution 4 to Figure 8-7 Format of 8-Bit Timer Mode Control Register 50 (TMC50)
and Figure 8-8 Format of 8-Bit Timer Mode Control Register 51 (TMC51)
• TOH0 pin output → TOH0 output, TOH1 pin output → TOH1 output
• Addition of TOH0, TOH1 output in block diagram
• Partial modification of description on PWM output
Addition of Notes 1 and 2 and Caution 3 to and modification of Note 3 in Figure 9-5 Format of 8-
Bit Timer H Mode Register 0 (TMHMD0)
Addition of Notes 1 and 2 and Caution 4 to Figure 9-6 Format of 8-Bit Timer H Mode Register
1 (TMHMD1)
Addition of Remark to Figure 9-13 Transfer Timing
Addition of Remark to Figure 9-15 Carrier Generator Mode Operation Timing
Addition of Note to Figure 10-2 Format of Watch Timer Operation Mode Register (WTM)
Modification of Remark in 11.4.3 Setting window open period of watchdog timer
Addition of Note 1 to Figure 12-2 Format of Clock Output Selection Register (CKS)
Modification of Figure 13-3 Format of A/D Converter Mode Register (ADM)
Modification of Table 13-1 Settings of ADCS and ADCE
Modification of Figure 13-4 Timing Chart When Comparator Is Used
Modification of Figure 14-1 Block Diagram of Serial Interface UART0
Addition of Note 1 to and modification of Note 2 in Figure 14-4 Format of Baud Rate Generator
Control Register 0 (BRGC0)
Addition of Notes 1 and 2 to Table 14-4 Set Value of TPS01 and TPS00
Modification of Figure 15-4 Block Diagram of Serial Interface UART6
Addition of Notes 1 and 2 to and modification of Note 3 in Figure 15-8 Format of Clock
Selection Register 6 (CKSR6)
Addition of Notes 1 and 2 to Table 15-4 Set Value of TPS63 to TPS60
Modification of Table 15-5 Set Data of Baud Rate Generator
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
Description
Classification
(a, c)
(b, c)
(b, c)
(b, c)
(a, c)
(b, c)
(b, c)
(b, c)
(b, c)
(b, c)
(b, c)
(b, c)
(b, c)
(a)
(a)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(2/5)
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