UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 767

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

5th edition
Edition
Addition of Caution 2, Note, and Remark 1 to 2.2.4 P30 to P33 (port 3)
Addition of Caution, Note, and Remark 1 to 2.2.9 P120 to P124 (port 12)
Addition of description to 2.2.16 V
Addition of following contents to Table 2-2 Pin I/O Circuit Types
• Addition of Notes 3 and 4 and Remark to P31/INTP2/OCD1A pin
• Addition of Notes 2 and 5 and Remark to P121/X1/OCD0A pin
• Addition of Note 4 to FLMD0 pin
• Change of connection of P121/X2/EXCLK/OCD0B to P124/XT2/EXCLKS
• Addition of connection of RESET pin when not used
Addition of Note 1 to Table 3-1 Set Values of Internal Memory Size Switching
Register (IMS) and Internal Expansion RAM Size Switching Register (IXS)
Addition of Remark and block number figure to Figures 3-1 Memory Map
(
Addition of Table 3-2 Correspondence Between Address Values and Block
Numbers of Flash Memory
Addition of Note 3 to Table 3-6 Special Function Register List (4/4)
Addition of 4.2 Difference in Representation of Memory Space
Change of setting of digital input and output in Table 5-4 Setting Functions of
P20/ANI0 to P27/ANI7 Pins
Addition of Caution to 5.2.3 Port 2
Addition of Caution 2, Note, and Remark 1 to 5.2.4 Port 3
Addition of Caution 2, Note, and Remark 1 to 5.2.9 Port 12
Addition of Caution to Figure 5-26 Format of Port Mode Register
Addition of Note to Figure 5-27 Format of Port Register
Deletion of Caution 2 in the previous edition from Figure 5-29 Format of A/D Port
Configuration Register (ADPC)
Change of setting of digital input and output in Table 5-6 Setting Functions of
ANI0/P20 to ANI7/P27 Pins
Addition of 5.6 Cautions on 1-Bit Manipulation Instruction for Port Register n
(Pn)
Addition of OR circuit to Figure 6-1 Block Diagram of Clock Generator
Change of Cautions 2 and 3 (description concerning stopping time of supplying CPU
clock) in Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL)
Addition of description of external clock input to 6.4.1 X1 oscillator and 6.4.2 XT1
oscillator
Change of voltage oscillation stabilization time and reset processing time in and
addition of Note 1 concerning waiting for oscillation accuracy stabilization to Figure 6-
12 Clock Generator Operation When Power Supply Voltage Is Turned On (When
1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Addition of Caution 1 and waiting time for oscillation accuracy stabilization to and
change of reset processing time in Figure 6-13 Clock Generator Operation When
Power Supply Voltage Is Turned On (When 2.7 V/1.59 V POC Mode Is Set
(Option Byte: POCMODE = 1))
Partial change (CPU clock supply stop time when AMPH = 1) of Note in 6.6.1 (1) <1>
Setting frequency (OSCCTL register) and 6.6.1 (2) <1> Setting frequency
(OSCCTL register)
µ
PD78F0531) to 3-8 Memory Map (
APPENDIX E REVISION HISTORY
DD
User’s Manual U17260EJ6V0UD
and EV
Description
µ
PD78F0537D)
DD
and 2.2.17 V
SS
and EV
SS
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 MEMORY
BANK SELECT
FUNCTION
(
AND 78F0537D ONLY)
CHAPTER 5 PORT
FUNCTIONS
CHAPTER 6 CLOCK
GENERATOR
µ
PD78F0536, 78F0537,
Chapter
(11/16)
767