UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 432

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
432
IICX0
CLX0
IICX0
CLX0
Bit 0
Bit 0
Notes 1. If the peripheral hardware clock (f
Caution Determine the transfer clock frequency of I
Remarks 1. ×:
0
0
0
0
0
0
0
0
0
1
1
1
1
The selection clock is set using a combination of bits 3, 1, and 0 (SMC0, CL01, and CL00) of IIC clock selection
register 0 (IICCL0) and bit 0 (CLX0) of IIC function expansion register 0 (IICX0).
SMC0
SMC0
Bit 3
Bit 3
2. If the peripheral hardware clock (f
0
1
0
0
0
0
1
1
1
0
1
1
1
2. f
3. f
operating frequency varies depending on the supply voltage.
• V
• V
• V
0), set CLX0, SMC0, CL01 and CL00 as follows.
enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0) to 1). To change
the transfer clock frequency, clear IICE0 once to 0.
IICCL0
IICCL0
CL01
CL01
Bit 1
Bit 1
DD
DD
DD
PRS
EXSCL0
0
0
0
0
1
1
0
1
1
×
0
1
1
= 4.0 to 5.5 V: f
= 2.7 to 4.0 V: f
= 1.8 to 2.7 V: f
:
:
CL00
CL00
Bit 0
Bit 0
0
×
0
1
0
1
×
0
1
×
×
0
1
don’t care
Peripheral hardware clock frequency
External clock frequency from EXSCL0 pin
f
f
f
f
f
f
f
f
f
Setting prohibited
f
f
Setting prohibited
PRS
PRS
PRS
PRS
PRS
EXSCL0
PRS
PRS
EXSCL0
PRS
PRS
/2
/2
/2
/2
/4
/2
/4
/2
/4
Selection Clock
Selection Clock
PRS
PRS
PRS
(f
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz (Standard and (A) grade products only)
W
CHAPTER 17 SERIAL INTERFACE IIC0
Table 17-2. Selection Clock Setting
(f
)
Notes 1, 2
W
)
User’s Manual U17260EJ6V0UD
PRS
PRS
) operates on the high-speed system clock (f
) operates on the internal high-speed oscillation clock (f
f
f
f
f
f
f
f
f
f
f
f
W
W
W
W
W
W
W
W
W
W
W
Transfer Clock
Transfer Clock
/44
/86
/86
/66
/24
/24
/18
/12
/12
/44
/24
(f
(f
W
W
/m)
/m)
2
C by using CLX0, SMC0, CL01, and CL00 before
2.00 to 4.19 MHz
4.19 to 8.38 MHz
6.4 MHz
4.00 to 8.38 MHz
6.4 MHz
4.00 to 4.19 MHz
3.8 MHz to 4.2 MHz
Settable Selection Clock
Settable Selection
Clock (f
(f
W
) Range
W
) Range
XH
) (XSEL = 1), the f
Normal mode
(SMC0 bit = 0)
High-speed mode
(SMC0 bit = 1)
High-speed mode
(SMC0 bit = 1)
Normal mode
(SMC0 bit = 0)
High-speed mode
(SMC0 bit = 1)
Operation Mode
Operation Mode
XH
) (XSEL =
PRS