UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 763

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

3rd edition
Edition
Modification of Caution 2 in Figure 16-5 Format of Serial Clock Selection
Register 10 (CSIC10)
Modification of Caution 2 in Figure 16-6 Format of Serial Clock Selection
Register 11 (CSIC11)
Modification of Note 1 of CSIM10 and CSIM11 in 16.4.1 (1) Register used
Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n
= 1 to Figure 16-11 Output Operation of First Bit
Addition of (b) Type 3: CKP1n = 1, DAP1n = 0 and (d) Type 4: CKP1n = 1, DAP1n
= 1 in Figure 16-12 Output Value of SO1n Pin (Last Bit)
Modification of Figure 17-1 Block Diagram of Serial Interface IIC0
Addition of Caution 2 to 17.2 (1) IIC shift register 0 (IIC0) and addition to
description in (2) Slave address register 0 (SVA0)
Addition of 17.2 (13) Stop condition generator
Addition of description to IICE0 and addition of Caution to Figure 17-5 Format of
IIC Control Register 0 (IICC0) (1/4)
Addition of Note 2 to Figure 17-5 Format of IIC Control Register 0 (IICC0) (2/4)
Addition of description to STT0 in Figure 17-5 Format of IIC Control Register 0
(IICC0) (3/4)
Addition of clearing condition to STCF and IICBSY in Figure 17-7 Format of IIC
Flag Register 0 (IICF0)
Modification of description in 17.3 (4) IIC clock selection register 0 (IICCL0)
Modification of description in 17.3 (6) I
Modification of Table 17-2 Selection Clock Setting
Addition of cause that ACK is not returned to 17.5.4 Acknowledge (ACK)
Addition of 17.5.7 Canceling wait
Modification of Table 17-6 Wait Periods and Figure 17-20 Communication
Reservation Timing
Modification of Table 17-7 Wait Periods
Addition of (4) to (6) to 17.5.15 Other cautions
Modification of 17.5.16 (1) Master operation (single-master system) and (2)
Master operation (multi-master system)
Modification of Figure 17-25 Slave Operation Flowchart (1) and Figure 17-26
Slave Operation Flowchart (2)
Addition of Note to (a) (i) When WTIM0 = 0 to and modification of (ii) When WTIM0
= 1 in 17.5.17 (1) Master device operation
Addition of Notes 1 to 3 to (b) (i) When WTIM0 = 0 in 17.5.17 (1) Master device
operation
Addition of Note to (c) (i) When WTIM0 = 0 in 17.5.17 (1) Master device
operation
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
Description
2
C transfer clock setting method
CHAPTER 16 SERIAL
INTERFACE CSI10,
CSI11
CHAPTER 17 SERIAL
INTERFACE IIC0
Chapter
(7/16)
763