UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 442

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

17.5.9 Address match detection method
address.
address has been set to slave address register 0 (SVA0) and when the address set to SVA0 matches the slave
address sent by the master device, or when an extension code has been received.
17.5.10 Error detection
(IIC0) of the transmitting device, so the IIC0 data prior to transmission can be compared with the transmitted IIC0 data
to enable detection of transmission errors. A transmission error is judged as having occurred when the compared
data values do not match.
442
(1) During address transmission/reception
(2) During data reception
(3) During data transmission
(4) Wait cancellation method
(5) Stop condition detection
In I
Address match can be detected automatically by hardware. An interrupt request (INTIIC0) occurs when a local
In I
2
2
C bus mode, the status of the serial data bus (SDA0) during data transmission is captured by IIC shift register 0
C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
• Slave device operation:
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
The four wait cancellation methods are as follows.
• Writing data to IIC shift register 0 (IIC0)
• Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
• Setting bit 1 (STT0) of IIC0 register (generating start condition)
• Setting bit 0 (SPT0) of IIC0 register (generating stop condition)
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellation.
INTIIC0 is generated when a stop condition is detected (only when SPIE0 = 1).
Note Master only.
Notes 1 and 2 above, regardless of the WTIM0 bit.
the WTIM0 bit.
Interrupt and wait timing are determined depending on the conditions described in
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17260EJ6V0UD
Note
Note