UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 303

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

11.4 Operation of Watchdog Timer
11.4.1 Controlling operation of watchdog timer
1.
2.
3.
4.
5.
Cautions 1. The first writing to WDTE after a reset release clears the watchdog timer, if it is made before
When the watchdog timer is used, its operation is specified by the option byte (0080H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1
• Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (0080H) (for details, see
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (0080H) (for
After a reset release, the watchdog timer starts counting.
By writing “ACH” to WDTE after the watchdog timer starts counting and before the overflow time set by the
option byte, the watchdog timer is cleared and starts counting again.
After that, write WDTE the second time or later after a reset release during the window open period. If WDTE
is written during a window close period, an internal reset signal is generated.
If the overflow time expires without “ACH” written to WDTE, an internal reset signal is generated.
A internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE)
• If data other than “ACH” is written to WDTE
• If the instruction is fetched from an area not set by the IMS and IXS registers (detection of an invalid check
• If the CPU accesses an area not set by the IMS and IXS registers (excluding FB00H to FFFFH) by executing
(the counter starts operating after a reset release) (for details, see CHAPTER 25).
11.4.2 and CHAPTER 25).
details, see 11.4.3 and CHAPTER 25).
during a CPU program loop)
a read/write instruction (detection of an abnormal access during a CPU program loop)
WDTON
0
1
2. If the watchdog timer is cleared by writing “ACH” to WDTE, the actual overflow time may be
3. The watchdog timer can be cleared immediately before the count value overflows (FFFFH).
the overflow time regardless of the timing of the writing, and the watchdog timer starts
counting again.
different from the overflow time set by the option byte by up to 2/f
Counter operation disabled (counting stopped after reset), illegal access detection operation disabled
Counter operation enabled (counting started after reset), illegal access detection operation enabled
Operation Control of Watchdog Timer Counter/Illegal Access Detection
CHAPTER 11 WATCHDOG TIMER
User’s Manual U17260EJ6V0UD
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seconds.
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