UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 733

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

16-bit
timer/event
counters
00, 01
Function
LVS0n, LVRn0
Timer start
errors
CR00n, CR01n:
16-bit timer
capture/compare
registers 00n,
01n
ES0n0, ES0n1
Re-triggering
one-shot pulse
OVF0n
One-shot pulse
output
TI00n
TI00n, TI01n
INTTM00n,
INTTM01n
CRC0n1 = 1
Specifying valid
edge after reset
Details of
Function
−
Be sure to set LVS0n and LVR0n following steps <1>, <2>, and <3> above.
Step <2> can be performed after <1> and before <3>.
Table 7-5 shows the restrictions for each channel.
An error of up to one clock may occur in the time required for a match signal to be
generated after timer start. This is because counting TM0n is started
asynchronously to the count pulse.
Set a value other than 0000H to CR00n and CR01n in clear & start mode entered
upon a match between TM0n and CR00n (TM0n cannot count one pulse when it is
used as an external event counter).
When the valid edge is input to the TI00n/TI01n pin and the reverse phase of the TI00n
pin is detected while CR00n/CR01n is read, CR01n performs a capture operation but
the read value of CR00n/CR01n is not guaranteed. At this time, an interrupt signal
(INTTM00n/INTTM01n) is generated when the valid edge of the TI00n/TI01n pin is
detected (the interrupt signal is not generated when the reverse-phase edge of the
TI00n pin is detected).
When the count value is captured because the valid edge of the TI00n/TI01n pin was
detected, read the value of CR00n/CR01n after INTTM00n/INTTM01n is generated.
The values of CR00n and CR01n are not guaranteed after 16-bit timer/event
counter 0n stops.
Set the valid edge of the TI00n pin while the timer operation is stopped (TMC0n3
and TMC0n2 = 00). Set the valid edge by using ES0n0 and ES0n1.
Make sure that the trigger is not generated while an active level is being output in
the one-shot pulse output mode. Be sure to input the next trigger after the current
active level is output.
The OVF0n flag is set to 1 in the following case, as well as when TM0n overflows.
Select the clear & start mode entered upon a match between TM0n and CR00n.
→ Set CR00n to FFFFH.
→ When TM0n matches CR00n and TM0n is cleared from FFFFH to 0000H
Even if the OVF0n flag is cleared to 0 after TM0n overflows and before the next
count clock is counted (before the value of TM0n becomes 0001H), it is set to 1
again and clearing is invalid.
One-shot pulse output operates correctly in the free-running timer mode or the
clear & start mode entered by the TI00n pin valid edge. The one-shot pulse cannot
be output in the clear & start mode entered upon a match between TM0n and
CR00n.
When the valid edge of TI00n is specified as the count clock, the capture register
for which TI00n is specified as a trigger does not operate correctly.
To accurately capture the count value, the pulse input to the TI00n and TI01n pins
as a capture trigger must be wider than two count clocks selected by PRM0n (see
Figure 7-9).
The capture operation is performed at the falling edge of the count clock but the
interrupt signals (INTTM00n and INTTM01n) are generated at the rising edge of the
next count clock (see Figure 7-9).
When the count value of the TM0n register is captured to the CR00n register in the
phase reverse to the signal input to the TI00n pin, the interrupt signal (INTTM00n)
is not generated after the count value is captured. If the valid edge is detected on
the TI01n pin during this operation, the capture operation is not performed but the
INTTM00n signal is generated as an external interrupt signal. Mask the INTTM00n
signal when the external interrupt is not used.
If the operation of the 16-bit timer/event counter 0n is enabled after reset and while
the TI00n or TI01n pin is at high level and when the rising edge or both the edges
are specified as the valid edge of the TI00n or TI01n pin, then the high level of the
TI00n or TI01n pin is detected as the rising edge. Note this when the TI00n or
TI01n pin is pulled up. However, the rising edge is not detected when the
operation is once stopped and then enabled again.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
Cautions
p. 246
p. 247
p. 247
p. 247
p. 248
p. 248
p. 248
p. 248
p. 249
p. 249
p. 249
p. 250
p. 250
p. 250
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p. 250
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