UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 337

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(1) Receive buffer register 0 (RXB0)
(2) Receive shift register 0 (RXS0)
(3) Transmit shift register 0 (TXS0)
This 8-bit register stores parallel data converted by receive shift register 0 (RXS0).
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 0 (RXS0).
If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is
always 0.
If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0.
RXB0 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.
Reset signal generation and POWER0 = 0 set this register to FFH.
This register converts the serial data input to the R
RXS0 cannot be directly manipulated by a program.
This register is used to set transmit data. Transmission is started when data is written to TXS0, and serial data is
transmitted from the T
TXS0 can be written by an 8-bit memory manipulation instruction. This register cannot be read.
Reset signal generation, POWER0 = 0, and TXE0 = 0 set this register to FFH.
Cautions 1. Set transmit data to TXS0 at least one base clock (f
2. Do not write the next transmit data to TXS0 before the transmission completion interrupt
signal (INTST0) is generated.
X
D0 pins.
CHAPTER 14 SERIAL INTERFACE UART0
User’s Manual U17260EJ6V0UD
X
D0 pin into parallel data.
XCLK0
) after setting TXE0 = 1.
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