UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 394

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

(1) Transmit buffer register 1n (SOTB1n)
394
SCK11/P04
Remark n = 0:
This register sets the transmit data.
Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial
operation mode register 1n (CSIM1n) is 1.
The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and
output to the serial output pin (SO1n).
SOTB1n can be written or read by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Cautions 1. Do not access SOTB1n when CSOT1n = 1 (during serial communication).
SI11/P03
f
f
f
f
f
f
n = 0, 1:
SSI11
2. In the slave mode, transmission/reception is started when data is written to SOTB11 with a
PRS
PRS
PRS
PRS
PRS
PRS
f
PRS
/2
/2
/2
/2
/2
/2
/2
low level input to the SSI11 pin. For details on the transmission/reception operation, see
16.4.2 (2) Communication operation.
2
3
4
5
6
7
(Available only in the
PM04
µ
µ
PD78F0531, 78F0532, 78F0533
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D
Transmit data
controller
Figure 16-2. Block Diagram of Serial Interface CSI11
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
Serial I/O shift
register 11 (SIO11)
Output latch
Clock start/stop controller &
(P04)
clock phase controller
Transmit controller
8
Baud rate generator
Internal bus
User’s Manual U17260EJ6V0UD
µ
Output latch
PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D)
Transmit buffer
register 11 (SOTB11)
8
selector
Output
INTCSI11
output
SO11
Output latch
(P02)
PM02
SSI11
SO11/P02