UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 143
UPD78F0537DGA(T)-9EV-A
Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0537DGA(T)-9EV-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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6.3 Registers Controlling Clock Generator
(1) Clock operation mode select register (OSCCTL)
Remarks 1. f
The following seven registers are used to control the clock generator.
• Clock operation mode select register (OSCCTL)
• Processor clock control register (PCC)
• Internal oscillation mode register (RCM)
• Main OSC control register (MOC)
• Main clock mode register (MCM)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
This register selects the operation modes of the high-speed system and subsystem clocks, and the gain of the
on-chip oscillator.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
2. f
3. f
4. f
5. f
6. f
7. f
8. f
9. f
10. f
11. f
X
RH
EXCLK
XH
XP
PRS
CPU
XT
EXCLKS
SUB
RL
:
:
:
:
:
:
:
:
:
:
: External subsystem clock frequency
X1 clock oscillation frequency
Internal high-speed oscillation clock frequency
External main system clock frequency
High-speed system clock frequency
Main system clock frequency
Peripheral hardware clock frequency
CPU clock frequency
XT1 clock oscillation frequency
Subsystem clock frequency
Internal low-speed oscillation clock frequency
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17260EJ6V0UD
143
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