UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 739

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

A/D
converter
Serial
interface
UART0
Function
Conversion
results just after
A/D conversion
start
A/D conversion
result register
(ADCR,
ADCRH) read
operation
UART mode
TXS0: Transmit
shift register 0
ASIM0:
Asynchronous
serial interface
operation mode
register 0
ASIS0:
Asynchronous
serial interface
reception error
status register 0
Details of
Function
The first A/D conversion value immediately after A/D conversion starts may not fall
within the rating range if the ADCS bit is set to 1 within 1
set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take measures such
as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
When a write operation is performed to the A/D converter mode register (ADM),
analog input channel specification register (ADS), and A/D port configuration
register (ADPC), the contents of ADCR and ADCRH may become undefined. Read
the conversion result following conversion completion before writing to ADM, ADS,
and ADPC. Using a timing other than the above may cause an incorrect conversion
result to be read.
If clock supply to serial interface UART0 is not stopped (e.g., in the HALT mode),
normal operation continues. If clock supply to serial interface UART0 is stopped
(e.g., in the STOP mode), each register stops operating, and holds the value
immediately before clock supply was stopped. The T
immediately before clock supply was stopped and outputs it. However, the
operation is not guaranteed after clock supply is resumed. Therefore, reset the
circuit so that POWER0 = 0, RXE0 = 0, and TXE0 = 0.
Set POWER0 = 1 and then set TXE0 = 1 (transmission) or RXE0 = 1 (reception) to
start communication.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may not
be initialized.
Set transmit data to TXS0 at least one base clock (f
Do not write the next transmit data to TXS0 before the transmission completion
interrupt signal (INTST0) is generated.
To start the transmission, set POWER0 to 1 and then set TXE0 to 1. To stop the
transmission, clear TXE0 to 0, and then clear POWER0 to 0.
To start the reception, set POWER0 to 1 and then set RXE0 to 1. To stop the
reception, clear RXE0 to 0, and then clear POWER0 to 0.
Set POWER0 to 1 and then set RXE0 to 1 while a high level is input to the RxD0
pin. If POWER0 is set to 1 and RXE0 is set to 1 while a low level is input, reception
is started.
TXE0 and RXE0 are synchronized by the base clock (f
enable transmission or reception again, set TXE0 or RXE0 to 1 at least two clocks
of base clock after TXE0 or RXE0 has been cleared to 0. If TXE0 or RXE0 is set
within two clocks of base clock, the transmission circuit or reception circuit may not
be initialized.
Set transmit data to TXS0 at least one base clock (f
Clear the TXE0 and RXE0 bits to 0 before rewriting the PS01, PS00, and CL0 bits.
Make sure that TXE0 = 0 when rewriting the SL0 bit. Reception is always
performed with “number of stop bits = 1”, and therefore, is not affected by the set
value of the SL0 bit.
Be sure to set bit 0 to 1.
The operation of the PE0 bit differs depending on the set values of the PS01 and
PS00 bits of asynchronous serial interface operation mode register 0 (ASIM0).
Only the first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 0 (RXB0) but discarded.
If data is read from ASIS0, a wait cycle is generated. Do not read data from ASIS0
when the CPU is operating on the subsystem clock and the peripheral hardware
clock is stopped. For details, see CHAPTER 35 CAUTIONS FOR WAIT.
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
Cautions
XCLK0
XCLK0
X
D0 pin also holds the value
XCLK0
XCLK0
) after setting TXE0 = 1.
) after setting TXE0 = 1.
µ
s after the ADCE bit was
) set by BRGC0. To
) set by BRGC0. To
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