UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 607

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Bit
manipulate
Instruction
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Group
2.
AND1
OR1
XOR1
SET1
CLR1
SET1
CLR1
NOT1
Mnemonic
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
control register (PCC).
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW. bit
CY, [HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
CY
CY
Operands
CHAPTER 28 INSTRUCTION SET
User’s Manual U17260EJ6V0UD
Bytes
3
3
2
3
2
3
3
2
3
2
3
3
2
3
2
2
3
2
2
2
2
3
2
2
2
1
1
1
Note 1
6
−
4
−
6
6
−
4
−
6
6
−
4
−
6
4
−
4
−
6
4
−
4
−
6
2
2
2
Clocks
Note 2
7
−
7
7
7
−
7
7
7
−
7
7
6
8
−
6
8
6
8
−
6
8
−
−
−
7
7
7
CY ← CY ∧ (saddr.bit)
CY ← CY ∧ sfr.bit
CY ← CY ∧ A.bit
CY ← CY ∧ PSW.bit
CY ← CY ∧ (HL).bit
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
CY ← CY ∨ (HL).bit
CY ← CY ∨ (saddr.bit)
CY ← CY ∨ sfr.bit
CY ← CY ∨ A.bit
CY ← CY ∨ PSW.bit
CY ← CY ∨ (HL).bit
(saddr.bit) ← 1
sfr.bit ← 1
A.bit ← 1
PSW.bit ← 1
(HL).bit ← 1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit ← 0
PSW.bit ← 0
(HL).bit ← 0
CY ← 1
CY ← 0
CY ← CY
CPU
) selected by the processor clock
Operation
Z AC CY
×
×
Flag
×
×
607
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
1
0
×