UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 543

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
oscillation clock (f
(when X1 oscillation
Internal reset signal
Internal high-speed
system clock (f
Notes 1.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 24
Remark V
V
V
DDPOC
Supply voltage
POC
High-speed
is selected)
= 1.59 V (TYP.)
= 2.7 V (TYP.)
1.8 V
2.
CPU
(V
RH
XH
Note 1
V
DD
0 V
LVI
)
)
V
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
)
The guaranteed operation range for the standard and (A) grade products is 1.8 V ≤ V
2.7 V ≤ V
operation range to the reset state when the supply voltage falls, use the reset function of the low-
voltage detector, or input a low level to the RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
Operation
LOW-VOLTAGE DETECTOR).
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
: LVI detection voltage
stops
: POC detection voltage
DD
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
≤ 5.5 V for the (A2) grade products. To set the voltage range below the guaranteed
Set LVI to be
used for reset
µ
oscillation clock)
(internal high-speed
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
Normal operation
specified by software.
Starting oscillation is
and Low-Voltage Detector (2/2)
User’s Manual U17260EJ6V0UD
Note 2
µ
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
µ
Normal operation
specified by software.
Starting oscillation is
Note 2
µ
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
µ
Normal operation
specified by software.
Starting oscillation is
Note 2
µ
DD
≤ 5.5 V, and
Operation stops
543