UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 351

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
(2) Generation of serial clock
14.4.4 Calculation of baud rate
(1) Baud rate calculation expression
(2) Error of baud rate
Notes 1. If the peripheral hardware clock (f
A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0).
Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0.
Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (f
counter.
The baud rate can be calculated by the following expression.
• Baud rate =
f
k:
The baud rate error can be calculated by the following expression.
• Error (%) =
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the
XCLK0
: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register
2. Note the following points when selecting the TM50 output as the base clock.
Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
TPS01
f
• V
• V
• V
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
• PWM mode (TMC506 = 1)
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
PRS
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
0
0
1
1
DD
DD
DD
operating frequency varies depending on the supply voltage.
reception destination.
Permissible baud rate range during reception.
f
2 × k
Actual baud rate (baud rate with error)
XCLK0
Desired baud rate (correct baud rate)
= 4.0 to 5.5 V: f
= 2.7 to 4.0 V: f
= 1.8 to 2.7 V: f
[bps]
TPS00
0
1
0
1
TM50 output
f
f
f
PRS
PRS
PRS
Table 14-4. Set Value of TPS01 and TPS00
PRS
PRS
PRS
CHAPTER 14 SERIAL INTERFACE UART0
/2
/2
/2
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz (Standard and (A) grade products only)
3
5
User’s Manual U17260EJ6V0UD
Note 2
PRS
1 MHz
250 kHz
62.5 kHz
f
PRS
) operates on the high-speed system clock (f
= 2 MHz
Base clock (f
− 1 × 100 [%]
2.5 MHz
625 kHz
156.25 kHz
f
PRS
XCLK0
= 5 MHz
) selection
f
5 MHz
1.25 MHz
312.5 kHz
PRS
Note 1
= 10 MHz
XCLK0
/8 to f
f
10 MHz
2.5 MHz
625 kHz
PRS
= 20 MHz
XCLK0
XH
) (XSEL = 1), the
/31) of the 5-bit
351