UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 542

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
<R>
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
542
oscillation clock (f
(when X1 oscillation
Internal reset signal
Internal high-speed
V
system clock (f
POC
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 24
Remark V
= 1.59 V (TYP.)
High-speed
is selected)
Supply voltage
1.8 V
Notes 1, 2, 3
CPU
2.
3.
4.
5.
RH
XH
(V
V
)
)
0 V
Operation
LVI
DD
LOW-VOLTAGE DETECTOR).
V
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
The guaranteed operation range for the standard and (A) grade products is 1.8 V ≤ V
2.7 V ≤ V
operation range to the reset state when the supply voltage falls, use the reset function of the low-
voltage detector, or input a low level to the RESET pin.
With the standard and (A) grade products, if the voltage rises to 1.8 V at a rate slower than 0.5 V/ms
(MIN.) on power application, input a low level to the RESET pin after power application and before the
voltage reaches 1.8 V, or set the 2.7 V/1.59 V POC mode by using an option byte (POCMODE = 1).
With the (A2) grade products, if the voltage rises to 2.7 V at a rate slower than 0.75 V/ms (MIN.) on
power application, input a low level to the RESET pin after power application and before the voltage
reaches 2.7 V.
The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
stops
: LVI detection voltage
: POC detection voltage
specified by software.
Starting oscillation is
Wait for voltage
(1.93 to 5.39 ms)
0.5 V/ms (MIN.)
Note 4
stabilization
Reset processing (11 to 45 s)
DD
≤ 5.5 V for the (A2) grade products. To set the voltage range below the guaranteed
Notes 2, 3
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
µ
and Low-Voltage Detector (1/2)
Note 5
User’s Manual U17260EJ6V0UD
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
used for interrupt
Reset processing (11 to 45 s)
Set LVI to be
oscillation clock)
(internal high-speed
µ
Normal operation
specified by software.
Starting oscillation is
Note 5
µ
Reset period
(oscillation
stop)
(1.93 to 5.39 ms)
Note 4
Wait for voltage
specified by software.
Starting oscillation is
stabilization
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
(internal high-speed
Normal operation
µ
Note 5
DD
≤ 5.5 V, and
Operation stops