UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 746

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

746
Interrupt
function
Key
interrupt
function
Standby
function
Function
MK0L, MK0H,
MK1L, MK1H:
Interrupt mask
flag registers
PR0L, PR0H,
PR1L, PR1H:
Priority
specification flag
registers
EGP, EGN:
External interrupt
rising edge,
falling edge
enable registers
Software
interrupt request
BRK instruction
KRM: Key return
mode register
Standby function
OSTC:
Oscillation
stabilization time
counter status
register
Details of
Function
Be sure to set bits 1 to 7 of MK1H to 1 for
Be sure to clear bits 4 to 7 of MK1H to 1 for
78F0537, and 78F0537D.
Be sure to set bits 1 to 7 of PR1H to 1 for
Be sure to clear bits 4 to 7 of PR1H to 1 for
78F0537, and 78F0537D.
Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Do not use the RETI instruction for restoring from the software interrupt.
The BRK instruction is not one of the above-listed interrupt request hold
instructions. However, the software interrupt activated by executing the BRK
instruction causes the IE flag to be cleared. Therefore, even if a maskable interrupt
request is generated during execution of the BRK instruction, the interrupt request is
not acknowledged.
If any of the KRM0 to KRM7 bits used is set to 1, set bits 0 to 7 (PU70 to PU77) of
the corresponding pull-up resistor register 7 (PU7) to 1.
If KRM is changed, the interrupt request flag may be set. Therefore, disable
interrupts and then change the KRM register. Clear the interrupt request flag and
enable interrupts.
The bits not used in the key interrupt mode can be used as normal ports.
The STOP mode can be used only when the CPU is operating on the main system
clock. The subsystem clock oscillation cannot be stopped. The HALT mode can be
used when the CPU is operating on either the main system clock or the subsystem
clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
After the above time has elapsed, the bits are set to 1 in order from MOST11 and
remain 1.
The oscillation stabilization time counter counts up to the oscillation stabilization
time set by OSTS. If the STOP mode is entered and then released while the
internal high-speed oscillation clock is being used as the CPU clock, set the
oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
OSTS
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
Cautions
µ
µ
PD78F0531, 78F0532, and 78F0533.
PD78F0531, 78F0532, and 78F0533.
µ
µ
PD78F0534, 78F0535, 78F0536,
PD78F0534, 78F0535, 78F0536,
p. 504
p. 505
p. 506
p. 510
p. 514
p. 516
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