UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 387

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

<R>
<R>
<R>
15.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
• Baud rate =
f
k:
XCLK6
Notes 1.
: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
TPS63
Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255)
0
0
0
0
0
0
0
0
1
1
1
1
2.
3.
f
2 × k
If the peripheral hardware clock (f
the f
• V
• V
• V
If the peripheral hardware clock (f
(XSEL = 0), when 1.8 V ≤ V
clock: f
Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50
• PWM mode (TMC506 = 1)
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
XCLK6
(TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the
duty = 50%.
DD
DD
DD
TPS62
PRS
Other than above
[bps]
0
0
0
0
1
1
1
1
0
0
0
0
= 4.0 to 5.5 V: f
= 2.7 to 4.0 V: f
= 1.8 to 2.7 V: f
PRS
operating frequency varies depending on the supply voltage.
) is prohibited.
TPS61
Table 15-4. Set Value of TPS63 to TPS60
CHAPTER 15 SERIAL INTERFACE UART6
0
0
1
1
0
0
1
1
0
0
1
1
PRS
PRS
PRS
≤ 20 MHz
≤ 10 MHz
≤ 5 MHz (Standard and (A) grade products only)
User’s Manual U17260EJ6V0UD
DD
TPS60
< 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base
0
1
0
1
0
1
0
1
0
1
0
1
PRS
PRS
) operates on the high-speed system clock (f
) operates on the internal high-speed oscillation clock (f
f
f
f
f
f
f
f
f
f
f
f
TM50 output
Setting prohibited
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
PRS
/2
/2
/2
/2
/2
/2
/2
/2
/2
/2
Note 2
2
3
4
5
6
7
8
9
10
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz
7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz
3.906 kHz 9.77 kHz
1.953 kHz 4.88 kHz
2 MHz
f
Base Clock (f
PRS
Note 3
=
5 MHz
2.5 MHz
1.25 MHz
625 kHz
312.5 kHz 625 kHz
156.25 kHz 312.5 kHz 625 kHz
5 MHz
f
PRS
XCLK6
=
) Selection
10 MHz
5 MHz
2.5 MHz
1.25 MHz
19.53 kHz 39.06 kHz
9.77 kHz
10 MHz
f
PRS
=
Note 1
20 MHz
10 MHz
5 MHz
2.5 MHz
1.25 MHz
19.53 kHz
20 MHz
XH
f
PRS
) (XSEL = 1),
=
387
RH
)