UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 744

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

744
Serial
interface
IIC0
Function
When
STCEN = 0
When
STCEN = 1
If other I
communications are
already in progress
Transfer clock
frequency setting
STT0, SPT0:
Bits 1, 0 of IIC control
register 0 (IICC0)
Transmission reserve When transmission is reserved, set SPIE0 (bit 4 of IICL0) to 1 so that an interrupt
Details of Function
2
C
Immediately after I
status (IICBSY (bit 6 of IICF0) = 1) is recognized regardless of the actual bus
status. When changing from a mode in which no stop condition has been
detected to a master device communication mode, first generate a stop condition
to release the bus, then perform master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has
not been detected).
Use the following sequence for generating a stop condition.
• Set IIC clock selection register 0 (IICCL0).
• Set bit 7 (IICE0) of IIC control register 0 (IICC0) to 1.
• Set bit 0 (SPT0) of IICC0 to 1.
Immediately after I
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the
first start condition (STT0 (bit 1 of IIC control register 0 (IICC0)) = 1), it is
necessary to confirm that the bus has been released, so as to not disturb other
communications.
If I
in progress when the SDA0 pin is low and the SCL0 pin is high, the macro of I
recognizes that the SDA0 pin has gone low (detects a start condition). If the
value on the bus at this time can be recognized as an extension code, ACK is
returned, but this interferes with other I
I
• Clear bit 4 (SPIE0) of IICC0 to 0 to disable generation of an interrupt request
• Set bit 7 (IICE0) of IICC0 to 1 to enable the operation of I
• Wait for detection of the start condition.
• Set bit 6 (LREL0) of IICC0 to 1 before ACK is returned (4 to 80 clocks after
Determine the transfer clock frequency by using SMC0, CL01, CL00 (bits 3, 1,
and 0 of IICL0), and CLX0 (bit 0 of IICX0) before enabling the operation (IICE0 =
1). To change the transfer clock frequency, clear IICE0 to 0 once.
Setting STT0 and SPT0 (bits 1 and 0 of IICC0) again after they are set and
before they are cleared to 0 is prohibited.
request is generated when the stop condition is detected. Transfer is started
when communication data is written to IIC0 after the interrupt request is
generated. Unless the interrupt is generated when the stop condition is
detected, the device stops in the wait state because the interrupt request is not
generated when communication is started. However, it is not necessary to set
SPIE0 to 1 when MSTS0 (bit 7 of IICS0) is detected by software.
2
C in the following sequence.
signal (INTIIC0) when the stop condition is detected.
setting IICE0 to 1), to forcibly disable detection.
2
C operation is enabled and the device participates in communication already
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
2
2
C operation is enabled (IICE0 = 1), the bus communication
C operation is enabled (IICE0 = 1), the bus released status
Cautions
2
C communications. To avoid this, start
2
C.
2
C
(18/25)
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