r5s72060w200fpv Renesas Electronics Corporation., r5s72060w200fpv Datasheet - Page 1006

• Manufacturer Part Number: r5s72060w200fpv
• Description: 32-bit Risc Microcomputer Superhtm Risc Engine Family / Sh7200 Series
• Manufacturer: Renesas Electronics Corporation.

Section 22 Power-Down Modes
22.3
22.3.1
(1)
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip modules
continue to run in sleep mode. Clock pulses continue to be output on the CKIO pin in clock mode
2.
(2)
Sleep mode is canceled by an interrupt (NMI, IRQ, and on-chip peripheral module), DMA address
error, or reset (manual reset or power-on reset).
• Canceling with an interrupt
• Canceling with a DMA address error
• Canceling with a reset
22.3.2
(1)
The LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR is 1. In software standby mode, not only the
CPU but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin
also halts in clock mode 2.
Rev. 2.00 Dec. 09, 2005 Page 982 of 1152
REJ09B0191-0200
When an NMI, IRQ, or on-chip peripheral module interrupt occurs, sleep mode is canceled and
interrupt exception handling is executed. When the priority level of the generated interrupt is
equal to or lower than the interrupt mask level that is set in the status register (SR) of the CPU,
or the interrupt by the on-chip peripheral module is disabled on the module side, the interrupt
request is not accepted and sleep mode is not canceled.
When a DMA address error occurs, sleep mode is canceled and DMA address error exception
handling is executed.
Sleep mode is canceled by a power-on reset or a manual reset.
Transition to Sleep Mode
Canceling Sleep Mode
Transition to Software Standby Mode
Operation
Sleep Mode
Software Standby Mode